Design of reversible Feynman and double Feynman gates in quantum-dot cellular automata nanotechnology

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sadat Riyaz ◽  
Vijay Kumar Sharma

Purpose This paper aims to propose the reversible Feynman and double Feynman gates using quantum-dot cellular automata (QCA) nanotechnology with minimum QCA cells and latency which minimizes the circuit area with the more energy efficiency. Design/methodology/approach The core aim of the QCA nanotechnology is to build the high-speed, energy efficient and as much smaller devices as possible. This brings a challenge for the designers to construct the designs that fulfill the requirements as demanded. This paper proposed a new exclusive-OR (XOR) gate which is then used to implement the logical operations of the reversible Feynman and double Feynman gates using QCA nanotechnology. Findings QCA designer-E has been used for the QCA designs and the simulation results. The proposed QCA designs have less latency, occupy less area and have lesser cell count as compared to the existing ones. Originality/value The latencies of the proposed gates are 0.25 which are improved by 50% as compared to the best available design as reported in the literature. The cell count in the proposed XOR gate is 11, while it is 14 in Feynman gate and 27 in double Feynman gate. The cell count for the proposed designs is minimum as compared to the best available designs.

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2707-2716

Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells


2019 ◽  
Vol 28 (08) ◽  
pp. 1950141 ◽  
Author(s):  
Haotian Chen ◽  
Hongjun Lv ◽  
Zhang Zhang ◽  
Xin Cheng ◽  
Guangjun Xie

Recently reported quantum-dot cellular automata (QCA) exclusive-OR gate designs are usually made with the AND–OR–INVERTER method in which it is difficult to optimize the XOR gate. This paper presents a novel low-power exclusive-OR (XOR) gate which is mainly based on cell-level format. Compared with the previous XOR gates, the proposed XOR gate performs in a different manner. This XOR gate design is accomplished by the intercellular effects method. For better performance comparison with previous relevant works, 4-, 8-, 16- and 32-bit parity generators are implemented in this paper. The simulation results show that there is a reduction of 32.5% cell count and 21.5% area in comparison with the existing advanced 32-bit parity generator. Especially in the aspect of clock cycle, the proposed design reduces the delay by 50% compared to the previous design. For simulation analysis, QCADesigner tool is used to verify the correctness of the proposed design. QCApro tool is used to evaluate the power dissipation of this design.


Author(s):  
A. Arunkumar Gudivada ◽  
K. Jayaram Kumar ◽  
Srinivasa Rao Jajula ◽  
Durga Prasad Siddani ◽  
Praveen Kumar Poola ◽  
...  

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