Heat flow analysis for EOS/ESD protection device design in SOI technology

1997 ◽  
Vol 44 (3) ◽  
pp. 464-471 ◽  
Author(s):  
P. Raha ◽  
S. Ramaswamy ◽  
E. Rosenbaum
Keyword(s):  
Heat Flow ◽  
Flow Analysis ◽  
Protection Device ◽  
Device Design ◽  
Esd Protection ◽  
Soi Technology

Conduction Uniformity Improvement of ESD Protection Device in 0.35 μm Partially-Depleted SOI Salicided CMOS Technology

2014 ◽  
Vol 687-691 ◽  
pp. 3251-3254
Author(s):  
Zhuo Tian ◽  
Bai Cheng Li
Keyword(s):  
Cmos Technology ◽  
Alpha Particles ◽  
Soft Error ◽  
Silicon On Insulator ◽  
Low Power Consumption ◽  
Protection Device ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Esd Protection ◽  
Soi Technology

ComparedtobulkCMOStechnology,Silicon-on-Insulator (SOI) CMOS technology has many advantages, such as low power consumption, low leakage current, low parasitic capacitance and a low soft error rate from both alpha particles and cosmic rays. However,electrostatic discharge (ESD) protection in SOI technology is still a major substantial barrier to overcome for the poor thermal conductivity of isolation oxide and the absence of vertical diode and silicon controlled rectifier (SCR).

ESD robustness prediction and protection device design in partially depleted SOI technology

1998 ◽  
Vol 38 (11) ◽  
pp. 1723-1731 ◽  
Author(s):  
P. Raha ◽  
J.C. Smith ◽  
J.W. Miller ◽  
E. Rosenbaum
Keyword(s):  
Protection Device ◽  
Device Design ◽  
Soi Technology

ESD protection device design using statistical methods

2002 ◽  
Vol 46 (12) ◽  
pp. 2117-2122 ◽  
Author(s):  
N Shigyo ◽  
H Kawashima ◽  
S Yasuda
Keyword(s):  
Statistical Methods ◽  
Protection Device ◽  
Device Design ◽  
Esd Protection
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