Design Optimization of High Voltage NPN ESD Protection Device in 130nm Power SOI Technology

2021 ◽  
Author(s):  
Raunak Kumar ◽  
Jie Zeng ◽  
Kyong Jin Hwang ◽  
Robert Gauthier
Keyword(s):  
Design Optimization ◽  
High Voltage ◽  
Protection Device ◽  
Esd Protection ◽  
Soi Technology

High-Voltage ESD Protection Device With Fast Transient Reaction and High Holding Voltage

2019 ◽  
Vol 66 (7) ◽  
pp. 2884-2891 ◽  
Author(s):  
Da-Wei Lai ◽  
Gijs de Raad ◽  
Stephen Sque ◽  
Wim Peters ◽  
Theo Smedes
Keyword(s):  
High Voltage ◽  
Protection Device ◽  
Esd Protection ◽  
Fast Transient

Using diode-stacked NMOS as high voltage tolerant ESD protection device for analog applications in deep submicron CMOS technologies

2003 ◽  
Vol 47 (5) ◽  
pp. 865-871 ◽  
Author(s):  
Chung-Hui Chen ◽  
Yean-Kuen Fang ◽  
Wen-De Wang ◽  
Chien-Chun Tsai ◽  
Shen Tu ◽  
...  
Keyword(s):  
High Voltage ◽  
Deep Submicron ◽  
Protection Device ◽  
Esd Protection ◽  
Submicron Cmos

Silicon Controlled Rectifier Based Partially Depleted SOI ESD Protection Device for High Voltage Application

2020 ◽  
Vol E103.C (4) ◽  
pp. 191-193
Author(s):  
Yibo JIANG ◽  
Hui BI ◽  
Hui LI ◽  
Zhihao XU ◽  
Cheng SHI
Keyword(s):  
High Voltage ◽  
Protection Device ◽  
Voltage Application ◽  
Esd Protection

Conduction Uniformity Improvement of ESD Protection Device in 0.35 μm Partially-Depleted SOI Salicided CMOS Technology

2014 ◽  
Vol 687-691 ◽  
pp. 3251-3254
Author(s):  
Zhuo Tian ◽  
Bai Cheng Li
Keyword(s):  
Cmos Technology ◽  
Alpha Particles ◽  
Soft Error ◽  
Silicon On Insulator ◽  
Low Power Consumption ◽  
Protection Device ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Esd Protection ◽  
Soi Technology

ComparedtobulkCMOStechnology,Silicon-on-Insulator (SOI) CMOS technology has many advantages, such as low power consumption, low leakage current, low parasitic capacitance and a low soft error rate from both alpha particles and cosmic rays. However,electrostatic discharge (ESD) protection in SOI technology is still a major substantial barrier to overcome for the poor thermal conductivity of isolation oxide and the absence of vertical diode and silicon controlled rectifier (SCR).

scholarly journals GDNMOS and GDBIMOS devices for high voltage ESD protection in thin film advanced FD-SOI technology

2019 ◽  
Vol 159 ◽  
pp. 90-98 ◽  
Author(s):  
Louise De Conti ◽  
Thomas Bedecarrats ◽  
Sorin Cristoloveanu ◽  
Maud Vinet ◽  
Philippe Galy
Keyword(s):  
Thin Film ◽  
High Voltage ◽  
Esd Protection ◽  
Soi Technology
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