Conduction Uniformity Improvement of ESD Protection Device in 0.35 μm Partially-Depleted SOI Salicided CMOS Technology

2014 ◽  
Vol 687-691 ◽  
pp. 3251-3254
Author(s):  
Zhuo Tian ◽  
Bai Cheng Li
Keyword(s):  
Cmos Technology ◽  
Alpha Particles ◽  
Soft Error ◽  
Silicon On Insulator ◽  
Low Power Consumption ◽  
Protection Device ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Esd Protection ◽  
Soi Technology

ComparedtobulkCMOStechnology,Silicon-on-Insulator (SOI) CMOS technology has many advantages, such as low power consumption, low leakage current, low parasitic capacitance and a low soft error rate from both alpha particles and cosmic rays. However,electrostatic discharge (ESD) protection in SOI technology is still a major substantial barrier to overcome for the poor thermal conductivity of isolation oxide and the absence of vertical diode and silicon controlled rectifier (SCR).

Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

ETRI Journal ◽  
2009 ◽  
Vol 31 (6) ◽  
pp. 725-731 ◽  
Author(s):  
Yong-Seo Koo ◽  
Kwangsoo Kim ◽  
Shihong Park ◽  
Kwidong Kim ◽  
Jong-Kee Kwon
Keyword(s):  
Leakage Current ◽  
Turn On ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Esd Protection ◽  
Protection Circuits

Reliability challenge of ESD protection: From planner SOI MOSFET to SOI FinFET

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740004 ◽  
Author(s):  
Yibo Jiang ◽  
Hui Bi ◽  
Liangwei Dong ◽  
Qinglong Li
Keyword(s):  
Electrostatic Discharge ◽  
Silicon On Insulator ◽  
Heat Conductor ◽  
Soi Mosfet ◽  
Novel Device ◽  
Thermal Distribution ◽  
Floating Base ◽  
Esd Protection ◽  
Tcad Simulation ◽  
Soi Technology

Implementation of Electrostatic Discharge (ESD) protection in Silicon on Insulator (SOI) technology is a challenge because of the inherent properties of poor heat conductor and heat trapping. In this paper, a novel device as ESD clamp is proposed as Fix-Base SOI FinFET clamp which addresses the troublesome problem of floating base. Moreover, its manufacturing process is compatible to the normal SOI process flow well. Finally, a detailed discussion including current density and thermal distribution are presented with the technique of 3D TCAD simulation.

Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology

2009 ◽  
Vol 40 (6) ◽  
pp. 1007-1012 ◽  
Author(s):  
Yongseo Koo ◽  
Kwangyeob Lee ◽  
Kuidong Kim ◽  
Jongki Kwon
Keyword(s):  
Cmos Technology ◽  
Deep Submicron ◽  
Protection Device ◽  
Esd Protection ◽  
Submicron Cmos

Influence of Body Contact on the ESD Protection Performance in 0.35μm Partially-Depleted SOI Salicided CMOS Technology

2011 ◽  
Vol 383-390 ◽  
pp. 7025-7031
Author(s):  
Zhong Fang Wang ◽  
Cheng Min Xie ◽  
Hong Ju Yue ◽  
Long Sheng Wu ◽  
You Bao Liu
Keyword(s):  
Transmission Line ◽  
Pulse Generator ◽  
Cmos Technology ◽  
Floating Body ◽  
Body Effect ◽  
Body Contact ◽  
Floating Body Effect ◽  
Gate Structure ◽  
Esd Protection ◽  
Soi Technology

Although body contact can solve the problem of floating body effect in the partially-depleted (PD) SOI technology, it still has important influence on the ESD protection performance. In order to investigate the influence of body contact on the ESD protection performance, three different structures are fabricated in 0.35μm PD SOI salicided CMOS technology, they are stick gate structure with body floating, H gate structure with body contact located outside the edge gate, and body tied source (BTS)structure with body contact placed intermittently along the source diffusion. The transmission line pulse generator(TLPG) measured results of these three different structures are compared and analyzed, both the stick gate structure with body floating and BTS structure have a better robustness level than H gate structure with body contact.

Polysilicon devices as a highly compatible ESD protection with modulable voltage and low capacitance

2021 ◽  
Vol 35 (04) ◽  
pp. 2150052
Author(s):  
yibo Jiang ◽  
Hui Bi ◽  
Zhihao Xu ◽  
Wei Zhao ◽  
Yuanyuan Zhang ◽  
...  
Keyword(s):  
Rf Power ◽  
Electronic Circuits ◽  
Rf Power Amplifier ◽  
Noise Coupling ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Esd Protection ◽  
Polysilicon Layer ◽  
Process Compatibility ◽  
Low Capacitance

The electronic circuits fabricated in a variety of technologies for different applications are all vulnerable to the electrostatic discharge (ESD) event. In this paper, polysilicon devices are investigated as ESD protection because of the noticeable advantages such as compatibility with several technologies, low parasitical capacitance, and little noise coupling. By forming the p-i-n diode in the polysilicon layer and stacking them together, the single polysilicon diode (SPD) and cascaded polysilicon diode (CasPD) are implemented in the 0.35 [Formula: see text] high voltage diffusion process. Through DC IV/CV, transmission line pulse (TLP), and zipping test, the CasPD presents as ESD protection for an S-band RF power amplifier, with high process-compatibility, modulable voltage, low leakage current and parasitic capacitance.

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

2017 ◽  
Vol 64 (10) ◽  
pp. 3979-3985 ◽  
Author(s):  
Jie-Ting Chen ◽  
Chun-Yu Lin ◽  
Ming-Dou Ker
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Protection Device ◽  
Esd Protection ◽  
On Chip
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