Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

IEEE Transactions on Components Packaging and Manufacturing Technology Part C ◽

10.1109/3476.739178 ◽

1998 ◽

Vol 21 (4) ◽

pp. 286-294 ◽

Author(s):

Karlheinz Bock ◽

Christian Russ ◽

Goncal Badenes ◽

Guido Groeseneken ◽

Ludo Deferm

Keyword(s):

Cmos Technology ◽

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A high performance 1.5 V, 0.10 μm gate length CMOS technology with scaled copper metallization

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) ◽

10.1109/iedm.1998.746526 ◽

2002 ◽

Author(s):

P. Gilbert ◽

I. Yang ◽

C. Pettinato ◽

M. Angyal ◽

B. Boeck ◽

...

Keyword(s):

High Performance ◽

Cmos Technology ◽

Copper Metallization ◽

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45-nm gate length CMOS technology and beyond using steep halo

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) ◽

10.1109/iedm.2000.904256 ◽

2002 ◽

Author(s):

H. Wakabayashi ◽

M. Ueki ◽

M. Narihiro ◽

T. Fukai ◽

N. Ikezawa ◽

...

Keyword(s):

Cmos Technology ◽

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A record high 150 GHz f/sub max/ realized at 0.18 μm gate length in an industrial RF-CMOS technology

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979471 ◽

2002 ◽

Author(s):

L.F. Tiemeijer ◽

H.M.J. Boots ◽

R.J. Havens ◽

A.J. Scholten ◽

P.H.W. de Vreede ◽

...

Keyword(s):

Cmos Technology ◽

Gate Length ◽

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A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology

2012 Symposium on VLSI Technology (VLSIT) ◽

10.1109/vlsit.2012.6242445 ◽

2012 ◽

Author(s):

U. Kwon ◽

K. Wong ◽

S. A. Krishnan ◽

L. Econimikos ◽

X. Zhang ◽

...

Keyword(s):

Cmos Technology ◽

Gate Length ◽

Low Resistance ◽

High K ◽

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A 1.2 V, 0.1 μm gate length CMOS technology: design and process issues

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) ◽

10.1109/iedm.1998.746435 ◽

2002 ◽

Author(s):

M. Rodder ◽

S. Hattangady ◽

N. Yu ◽

W. Shiau ◽

P. Nicollian ◽

...

Keyword(s):

Cmos Technology ◽

Gate Length ◽

Technology Design

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A 70 nm gate length CMOS technology with 1.0 V operation

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) ◽

10.1109/vlsit.2000.852750 ◽

2002 ◽

Author(s):

A. Ono ◽

K. Fukasaku ◽

T. Matsuda ◽

T. Fukai ◽

N. Ikezawa ◽

...

Keyword(s):

Cmos Technology ◽

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Influence Of Well Profile And Gate Length On The ESD Performance Of A Fully Silicided 0.25/spl mu/m Cmos Technology

1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium ◽

10.1109/eosesd.1997.634258 ◽

1997 ◽

Author(s):

K. Bock ◽

C. Russ ◽

G. Badenes ◽

G. Groeseneken ◽

L. Deferm

Keyword(s):

Cmos Technology ◽

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Influence of gate length on ESD-performance for deep submicron CMOS technology

Microelectronics Reliability ◽

10.1016/s0026-2714(00)00243-2 ◽

2001 ◽

Vol 41 (3) ◽

pp. 375-383 ◽

Author(s):

K. Bock ◽

B. Keppens ◽

V.De Heyn ◽

G. Groeseneken ◽

L.Y. Ching ◽

...

Keyword(s):

Cmos Technology ◽

Deep Submicron ◽

Gate Length ◽

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Gate length scaling of high-k vertical MOSFET toward 20nm CMOS technology and beyond

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2013.6716557 ◽

2013 ◽

Author(s):

Takeshi Sasaki ◽

Tetsuo Endoh

Keyword(s):

Cmos Technology ◽

Gate Length ◽

High K ◽

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A 0.10 μm gate length CMOS technology with 30 Å gate dielectric for 1.0 V-1.5 V applications

International Electron Devices Meeting. IEDM Technical Digest ◽

10.1109/iedm.1997.650349 ◽

2002 ◽

Author(s):

M. Rodder ◽

M. Hanratty ◽

D. Rogers ◽

T. Laaksonen ◽

J.C. Hu ◽

...

Keyword(s):

Gate Dielectric ◽

Cmos Technology ◽

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