FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field

With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

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High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field Along with RSA Comparison

International Journal of Advanced Research in Science, Communication and Technology ◽

10.48175/ijarsct-1819 ◽

2021 ◽

pp. 117-123

Author(s):

Mrs. Lakshmidevi TR ◽

Ms. Kavana Shree C ◽

Ms. Arshitha S ◽

Ms. Kavya L

Keyword(s):

Elliptic Curve ◽

High Speed ◽

Single Point ◽

Prime Field ◽

Point Multiplication ◽

Field Programmable ◽

Critical Requirement ◽

Edwards Curve ◽

The Impact ◽

Twisted Edwards Curve

Creating a high-speed elliptic curve cryptographic (ECC) processor capable of performing fast point Multiplication with low hardware utilisation is a critical requirement in cryptography and network security. This paper describes the implementation of a high-speed, field-programmable gate array (FPGA) in this paper. A high-security digital signature technique is implemented using Edwards25519, a recently approved twisted Edwards’s curve. For point addition and point doubling operations on the twisted Edwards curve, advanced hardware configurations are developed in which each task involves only 516 and 1029 clock cycles, respectively. As an observation the ECC processor presented in this paper begins with the process which takes 1.48 ms of single-point multiplication to be performed. The comparison of key size and its ratio which shows the impact on processing of each processor is shown for ECC processor and RSA processor. The delay and number of slices used for the ECC processor is shown and this is a developed solution saves time by providing rapid scalar multiplication with low hardware consumption without compromising on security.

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A High-Speed Elliptic Curve Cryptography Processor for Teleoperated Systems Security

Mathematical Problems in Engineering ◽

10.1155/2021/6633925 ◽

2021 ◽

Vol 2021 ◽

pp. 1-8

Author(s):

Yong Xiao ◽

Weibin Lin ◽

Yun Zhao ◽

Chao Cui ◽

Ziwen Cai

Keyword(s):

Elliptic Curve ◽

Elliptic Curve Cryptography ◽

High Speed ◽

High Performance ◽

Prime Field ◽

Practical Applications ◽

Cell Library ◽

Cryptographic Algorithm ◽

Human Operators ◽

Key Length

Teleoperated robotic systems are those in which human operators control remote robots through a communication network. The deployment and integration of teleoperated robot’s systems in the medical operation have been hampered by many issues, such as safety concerns. Elliptic curve cryptography (ECC), an asymmetric cryptographic algorithm, is widely applied to practical applications because its far significantly reduced key length has the same level of security as RSA. The efficiency of ECC on GF (p) is dictated by two critical factors, namely, modular multiplication (MM) and point multiplication (PM) scheduling. In this paper, the high-performance ECC architecture of SM2 is presented. MM is composed of multiplication and modular reduction (MR) in the prime field. A two-stage modular reduction (TSMR) algorithm in the SCA-256 prime field is introduced to achieve low latency, which avoids more iterative subtraction operations than traditional algorithms. To cut down the run time, a schedule is put forward when exploiting the parallelism of multiplication and MR inside PM. Synthesized with a 0.13 um CMOS standard cell library, the proposed processor consumes 341.98k gate areas, and each PM takes 0.092 ms.

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Memory Compact High-Speed QC-LDPC Decoder Based on FPGA

Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University ◽

10.1051/jnwpu/20193730515 ◽

2019 ◽

Vol 37 (3) ◽

pp. 515-522

Author(s):

Tianjiao Xie ◽

Bo Li ◽

Mao Yang ◽

Zhongjiang Yan

Keyword(s):

High Speed ◽

Clock Cycle ◽

Fpga Implementation ◽

Maximum Frequency ◽

Ldpc Decoder ◽

Memory Strategies ◽

Multiple Data ◽

Decoder Architecture ◽

Place And Route ◽

Area Efficient

In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle so as to increase the throughput of decoder. We demonstrate significant high speed and area efficient benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. The result shows that our new decoder can operate at a maximum frequency of 250 MHz after place and route, and achieve a throughput up to 2 Gb/s at 14 iterations.

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