scholarly journals High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field Along with RSA Comparison

2021 ◽  
pp. 117-123
Author(s):  
Mrs. Lakshmidevi TR ◽  
Ms. Kavana Shree C ◽  
Ms. Arshitha S ◽  
Ms. Kavya L
Keyword(s):  
Elliptic Curve ◽  
High Speed ◽  
Single Point ◽  
Prime Field ◽  
Point Multiplication ◽  
Field Programmable ◽  
Critical Requirement ◽  
Edwards Curve ◽  
The Impact ◽  
Twisted Edwards Curve

Creating a high-speed elliptic curve cryptographic (ECC) processor capable of performing fast point Multiplication with low hardware utilisation is a critical requirement in cryptography and network security. This paper describes the implementation of a high-speed, field-programmable gate array (FPGA) in this paper. A high-security digital signature technique is implemented using Edwards25519, a recently approved twisted Edwards’s curve. For point addition and point doubling operations on the twisted Edwards curve, advanced hardware configurations are developed in which each task involves only 516 and 1029 clock cycles, respectively. As an observation the ECC processor presented in this paper begins with the process which takes 1.48 ms of single-point multiplication to be performed. The comparison of key size and its ratio which shows the impact on processing of each processor is shown for ECC processor and RSA processor. The delay and number of slices used for the ECC processor is shown and this is a developed solution saves time by providing rapid scalar multiplication with low hardware consumption without compromising on security.

scholarly journals Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5148
Author(s):  
Md. Mainul Islam ◽  
Md. Selim Hossain ◽  
Moh. Khalid Hasan ◽  
Md. Shahjalal ◽  
Yeong Min Jang
Keyword(s):  
Elliptic Curve ◽  
High Speed ◽  
High Performance ◽  
Security Level ◽  
Prime Field ◽  
Iot Security ◽  
Point Multiplication ◽  
Low Area ◽  
Edwards Curve ◽  
Twisted Edwards Curve

With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

scholarly journals FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 178811-178826 ◽  
Author(s):  
Md. Mainul Islam ◽  
Md. Selim Hossain ◽  
Moh. Khalid Hasan ◽  
Md. Shahjalal ◽  
Yeong Min Jang
Keyword(s):  
Elliptic Curve ◽  
High Speed ◽  
Fpga Implementation ◽  
Prime Field ◽  
Point Multiplication ◽  
Area Efficient

scholarly journals A High-Speed Elliptic Curve Cryptography Processor for Teleoperated Systems Security

2021 ◽  
Vol 2021 ◽  
pp. 1-8
Author(s):  
Yong Xiao ◽  
Weibin Lin ◽  
Yun Zhao ◽  
Chao Cui ◽  
Ziwen Cai
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
High Speed ◽  
High Performance ◽  
Prime Field ◽  
Practical Applications ◽  
Cell Library ◽  
Cryptographic Algorithm ◽  
Human Operators ◽  
Key Length

Teleoperated robotic systems are those in which human operators control remote robots through a communication network. The deployment and integration of teleoperated robot’s systems in the medical operation have been hampered by many issues, such as safety concerns. Elliptic curve cryptography (ECC), an asymmetric cryptographic algorithm, is widely applied to practical applications because its far significantly reduced key length has the same level of security as RSA. The efficiency of ECC on GF (p) is dictated by two critical factors, namely, modular multiplication (MM) and point multiplication (PM) scheduling. In this paper, the high-performance ECC architecture of SM2 is presented. MM is composed of multiplication and modular reduction (MR) in the prime field. A two-stage modular reduction (TSMR) algorithm in the SCA-256 prime field is introduced to achieve low latency, which avoids more iterative subtraction operations than traditional algorithms. To cut down the run time, a schedule is put forward when exploiting the parallelism of multiplication and MR inside PM. Synthesized with a 0.13 um CMOS standard cell library, the proposed processor consumes 341.98k gate areas, and each PM takes 0.092 ms.

Brain Deformation in Linear Head Impact

2009 ◽  
Author(s):  
Kaveh Laksari ◽  
Kurosh Darvish
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Single Point ◽  
Arbitrary Lagrangian Eulerian ◽  
Brain Deformation ◽  
Ale Formulation ◽  
Point Integration ◽  
Inertial Loading ◽  
Experimental Values ◽  
The Impact

In this study, a 2D model of the head underwent linear impact and the experiments were simulated by finite element models. A cylinder with a diameter of 100mm and height of 20mm was filled with 5% gelatin, which was used as the brain surrogate material. The physical model was mounted onto a High Speed Computer Controlled Impact System to generate inertial loading of approximately 50 G average deceleration. The deformation of the samples was studied through image processing. Finite element (FE) analysis was used to simulate the experiments. The impact tests were modeled with two methods: a Lagrangian formulation with single point integration and an Arbitrary Lagrangian Eulerian (ALE) formulation with single point integration and void using LS-Dyna FE code. In the model with slip contact, the normal and shear strains reached more than 20% in some regions, which confirmed the risk of axonal injury in the linear impacts applied in this study. It was seen that in the Lagrangian models, in order to stabilize the simulation, high bulk moduli needed to be used; however, this resulted in much smaller void generation in the posterior region of the model. It was shown that the void generation reaches the experimental values by introducing 1–2 mm initial gaps between brain and skull. The ALE model was more stable and less sensitive to the bulk modulus, but showed smaller deformations.

scholarly journals Improved throughput of Elliptic Curve Digital Signature Algorithm (ECDSA) processor implementation over Koblitz curve k-163 on Field Programmable Gate Array (FPGA)

2020 ◽  
Vol 17 (3(Suppl.)) ◽  
pp. 1029
Author(s):  
Firas Ghanim Tawfeeq ◽  
Alaa M. Abdul-Hadi
Keyword(s):  
Elliptic Curve ◽  
Digital Signature ◽  
High Speed ◽  
Performance Metrics ◽  
Efficient Design ◽  
Digital Signature Algorithm ◽  
Field Programmable ◽  
And Performance ◽  
Time Required ◽  
Performance Challenges

            The widespread use of the Internet of things (IoT) in different aspects of an individual’s life like banking, wireless intelligent devices and smartphones has led to new security and performance challenges under restricted resources. The Elliptic Curve Digital Signature Algorithm (ECDSA) is the most suitable choice for the environments due to the smaller size of the encryption key and changeable security related parameters. However, major performance metrics such as area, power, latency and throughput are still customisable and based on the design requirements of the device. The present paper puts forward an enhancement for the throughput performance metric by proposing a more efficient design for the hardware implementation of ECDSA. The design raised the throughput to 0.08207 Mbit/s, leading to an increase of 6.95% from the existing design. It also includes the design and implementation of the Universal Asynchronous Receiver Transmitter (UART) module. The present work is based on a 163-bit key-size over Koblitz curve k-163 and secure hash function SHA-1. A serial module for the underlying modular layer, high-speed architecture of Koblitz point addition and Koblitz point multiplication have been considered in this work, in addition to utilising the carry-save-multiplier, modular adder-subtractor and Extended Euclidean module for ECDSA protocols. All modules are designed using VHDL and implemented on the platform Virtex5 xc5vlx155t-3ff1738. Signature generation requires 0.55360ms, while its validation consumes 1.10947288ms. Thus, the total time required to complete both processes is equal to 1.66ms and the maximum frequency is approximately 83.477MHZ, consuming a power of 99mW with the efficiency approaching 3.39 * 10-6.

Redundant-Signed-Digit-Based High Speed Elliptic Curve Cryptographic Processor

2019 ◽  
Vol 28 (05) ◽  
pp. 1950081 ◽  
Author(s):  
Yasir A. Shah ◽  
Khalid Javeed ◽  
Shoaib Azmat ◽  
Xiaojun Wang
Keyword(s):  
Elliptic Curve ◽  
High Speed ◽  
Clock Cycle ◽  
Propagation Delay ◽  
System Level ◽  
Modular Arithmetic ◽  
Pipelined Architecture ◽  
Field Programmable ◽  
Cycle Count ◽  
Modular Multiplier

In this paper, a high speed elliptic curve cryptographic (ECC) processor for National Institute of Standards and Technology (NIST) recommended prime [Formula: see text] is proposed. The modular arithmetic components in the proposed ECC processor are highly optimized at both architectural level and circuit level. Redundant-signed-digit (RSD) arithmetic is adopted in the modular arithmetic components to avoid lengthy carry propagation delay. A high speed modular multiplier is designed based on an efficient segmentation and pipelining strategy. The clock cycle count is reduced as result of the segmentation, whereas operating frequency and throughput are significantly increased due to the pipelining. An optimized pipelined architecture for modular division is also presented which is suitable for the design of ECC processor using projective coordinates. The Joye’s double and add (DAA) algorithm based on [Formula: see text]-only common [Formula: see text] (co-[Formula: see text]) coordinate is adopted at the system level for its regular and efficient behavior. The proposed ECC processor is flexible and can be implemented using any field programmable gate array (FPGA) family or standard cell libraries. The proposed ECC processor executes a single elliptic curve (EC) point multiplication (PM) operation in 0.47[Formula: see text]ms at a maximum frequency of 327[Formula: see text]MHz on Virtex-6 FPGA. The implementation results demonstrate that the proposed ECC processor outperforms the other contemporary designs reported in the literature in terms of speed and [Formula: see text] metrics.

Surface and Microstructure Considerations in High Speed Single Point Incremental Forming of Ti6Al4V Sheets

2014 ◽  
Vol 611-612 ◽  
pp. 1071-1078 ◽  
Author(s):  
Giuseppina Ambrogio ◽  
Stefania Bruschi ◽  
Francesco Gagliardi ◽  
Andrea Ghiotti ◽  
Luigino Filice
Keyword(s):  
Metal Forming ◽  
High Speed ◽  
Incremental Forming ◽  
Single Point ◽  
Heating Source ◽  
The Past ◽  
Process Configuration ◽  
Experimental Campaign ◽  
Application Potential ◽  
The Impact

Flexible sheet metal forming processes represent a big challenge, which involved a number of researchers all over the world in the last decades. Among these, Incremental Sheet Forming (ISF) process is one of the most investigated and promising due to its simplicity, cheapness and applicability. Furthermore, the possibility to increase the process velocity makes the ISF more suitable than in the past; as a consequence, its application potential is surely increased. It was already highlighted that high speed significantly raises the process temperature, improving the workability of Titanium alloys. In this process configuration, no further heating source is strictly required because the temperature increase is generated due to the plastic deformation and the friction conditions at the interface between the punch and the sheet. While the process feasibility has been already investigated, a lack of knowledge in the literature is present focusing on the analysis of the process impact on the material properties. Accordingly, an experimental campaign on Ti6Al4V sheets has been performed, considering a punch speed two orders of magnitude higher than the conventionally used one. The obtained surfaces have been compared to sheets worked by traditional velocity in order to accurately analyze the impact of high speed. Furthermore, microstructural analyses have been carried out confirming the high speed suitability. All the details are reported in the manuscript

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