An Asymmetric Modular Multicell Inverter with Low Number of DC Source and Voltage Stress

2006 ◽

Author(s):

Tsung-Te Li ◽

Chao-Chi Wu ◽

Jung-Hsiang Chuang ◽

Jon C. Lee

Keyword(s):

Failure Analysis ◽

Electrical Characterization ◽

Physical Analysis ◽

Gate Leakage ◽

Force Microscopy ◽

Atomic Force ◽

Transmission Electron ◽

Voltage Stress ◽

Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

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Analysis of Induced End-of-Life Failures in SRAM Through Nanoprobing

10.31399/asm.cp.istfa2018p0387 ◽

2018 ◽

Author(s):

Oberon Dixon-Luinenburg ◽

Jordan Fine

Keyword(s):

End Of Life ◽

Soft Errors ◽

Cause Analysis ◽

New Approach ◽

Performance Loss ◽

Root Cause ◽

Long Period ◽

Atomic Force ◽

Stress Resultant ◽

Voltage Stress

Abstract In this paper, we demonstrate a novel nanoprobing approach to establish cause-and-effect relationships between voltage stress and end-of-life performance loss and failure in SRAM cells. A Hyperion II Atomic Force nanoProber was used to examine degradation for five 6T cells on an Intel 14 nm processor. Ten minutes of asymmetrically applied stress at VDD=2 V was used to simulate a ‘0’ bit state held for a long period, subjecting each pullup and pulldown to either VDS or VGS stress. Resultant degradation caused read and hold margins to be reduced by 20% and 5% respectively for the ‘1’ state and 5% and 2% respectively for the ‘0’ state. ION was also reduced, for pulldown and pullup respectively, by 4.5% and 5.4% following VGS stress and 2.6% and 33.8% following VDS stress. Negative read margin failures, soft errors, and read time failures all become more prevalent with these aging symptoms whereas write stability is improved. This new approach enables highly specific root cause analysis and failure prediction for end-of-life in functional on-product SRAM.

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Effect of System Grounding, AC-DC Converter Topology and Inverter Modulation on Motor Insulation Voltage Stress

2020 IEEE Energy Conversion Congress and Exposition (ECCE) ◽

10.1109/ecce44975.2020.9235646 ◽

2020 ◽

Author(s):

G. Y. Sizov ◽

Z. Vrankovic ◽

M. J. Melfi ◽

G. L. Skibinski ◽

Zhijun Liu

Keyword(s):

Voltage Stress ◽

Converter Topology

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A Single Switch High Gain DC-DC converter with Reduced Voltage Stress

2020 IEEE 7th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON) ◽

10.1109/upcon50219.2020.9376578 ◽

2020 ◽

Author(s):

Shahrukh Khan ◽

Mohammad Zaid ◽

Arshad Mahmood ◽

Javed Ahmad ◽

Afroz Alam

Keyword(s):

High Gain ◽

Voltage Stress

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Novel High-Efficiency High Step-Up DC–DC Converter with Soft Switching and Low Component Voltage Stress for Photovoltaic System

Processes ◽

10.3390/pr9071112 ◽

2021 ◽

Vol 9 (7) ◽

pp. 1112

Author(s):

Yu-En Wu ◽

Jyun-Wei Wang

Keyword(s):

High Voltage ◽

Output Voltage ◽

High Efficiency ◽

Low Voltage ◽

Leakage Inductance ◽

Power Switch ◽

Half Wave Voltage ◽

Half Wave ◽

Voltage Stress ◽

Voltage Doubler

This study developed a novel, high-efficiency, high step-up DC–DC converter for photovoltaic (PV) systems. The converter can step-up the low output voltage of PV modules to the voltage level of the inverter and is used to feed into the grid. The converter can achieve a high step-up voltage through its architecture consisting of a three-winding coupled inductor common iron core on the low-voltage side and a half-wave voltage doubler circuit on the high-voltage side. The leakage inductance energy generated by the coupling inductor during the conversion process can be recovered by the capacitor on the low-voltage side to reduce the voltage surge on the power switch, which gives the power switch of the circuit a soft-switching effect. In addition, the half-wave voltage doubler circuit on the high-voltage side can recover the leakage inductance energy of the tertiary side and increase the output voltage. The advantages of the circuit are low loss, high efficiency, high conversion ratio, and low component voltage stress. Finally, a 500-W high step-up converter was experimentally tested to verify the feasibility and practicability of the proposed architecture. The results revealed that the highest efficiency of the circuit is 98%.

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