A CMOS sub-harmonic passive mixer having low flicker noise with back-gate coupling LC tank Quadrature VCO

Author(s):  
Jaeseok Lee ◽  
Jihyun Park ◽  
Sanghyun Choi ◽  
Sangho Lee ◽  
Hyeongdong Kim
2017 ◽  
Vol 26 (11) ◽  
pp. 1750184 ◽  
Author(s):  
Qiuzhen Wan ◽  
Jun Dong ◽  
Hui Zhou ◽  
Fei Yu

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6[Formula: see text]mW under a 0.8[Formula: see text]V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04[Formula: see text]GHz as the tuning voltage is varied from 0.8 to 0.0[Formula: see text]V. The phase noise is [Formula: see text]118.3[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency from the carrier frequency of 2.36[Formula: see text]GHz and the corresponding figure-of-merit of the QVCO is [Formula: see text]183.7[Formula: see text]dBc/Hz.


2020 ◽  
Vol 100 ◽  
pp. 104784
Author(s):  
Emad Ebrahimi ◽  
Sasan Naseh ◽  
Ali Ebrahimi ◽  
Mohammad Maymandi-Nejad

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1369
Author(s):  
Dongquan Huo ◽  
Luhong Mao ◽  
Liji Wu ◽  
Xiangmin Zhang

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.


2010 ◽  
Vol 52 (12) ◽  
pp. 2682-2685
Author(s):  
Mei-Ling Yeh ◽  
Yao-Chian Lin ◽  
Wan-Rone Liou ◽  
Sheng-Hing Kuo ◽  
Patrick Roblin ◽  
...  

PIERS Online ◽  
2007 ◽  
Vol 3 (7) ◽  
pp. 971-975 ◽  
Author(s):  
Yu-Ching Tsai ◽  
Yi-Shing Shen ◽  
C. F. Jou
Keyword(s):  

2015 ◽  
Vol 34 (10) ◽  
pp. 3147-3160 ◽  
Author(s):  
Qiuzhen Wan ◽  
Yaneng Liu ◽  
Qingdi Wang
Keyword(s):  

Author(s):  
Hye-Ryoung Kim ◽  
Seung-Min Oh ◽  
Sung-Do Kim ◽  
Young-Sik Youn ◽  
Sang-Gug Lee
Keyword(s):  

Author(s):  
Hassene Mnif ◽  
Dorra Mellouli ◽  
Mourad Loulou

This chapter describes the design and the optimization of Quadrature Voltage Controlled Oscillators (QVCOs) based on the coupling of two LC-tank VCO. This work covers the phase noise analysis, a graphical optimization approach, already used to optimize LC oscillator phase noise (Andreani, Bonfanti, Romano, & Samori, 2002), to optimize QVCO phase noise while satisfying design constraints such as power dissipation, tank amplitude, tuning range and start up condition. The cross-coupling transistors impact on phase noise for different configurations is especially addressed. The obtained BS-QVCO, using 0.35µm CMOS process, can be tuned between 2.2GHz and 2.58GHz, and shows a phase noise of -129 dBc/Hz at 1MHz offset from a 2.4 GHz carrier, for a current consumption of 9.25mW. The equivalent phase error and amplitude error between I and Q signals are respectively 0.65° and 1.87%.


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