Inventions of Monolithic Microwave Integrated Circuits

This chapter deals with the concept of first time right IC. A development of subsystems for wireless application is used as test case. The subsystems are Low Noise Amplifier (LNA), Medium Power Amplifier (MPA) and Variable Signal Generator (VSG). Several issues such as suitable multiband design flow and high speed switch must be solved. A new design methodology of integrated circuits for multiband application is presented. The design methodology is modified from a typical Monolithic Microwave Integrated Circuit (MMIC) flow. Core based design, parasitic aware approach and power constrained optimization are introduced into the new design flow. The same core circuit topology is used as main block to design 2.4 GHz and 3.5 GHz LNA and MPA. A power constrained optimization is applied to a test case amplifier i.e. broadband amplifier to get the optimized RF performance. The optimization is simulation-based technique. A 0.15 µm 85 GHz PHEMT is used in designing the LNA, MPA and broadband amplifier. This chapter also introduces the inventions of Voltage Controlled Oscillator (VCO), Mixer, Low Noise Amplifiers (LNA), Power Amplifiers (PA) and Transmit-Receive Switch (T/R). These circuits are crucial components for RF and Microwave front-end integrated circuits. The elements of inventions of circuits are clearly explained. The inventions reflect the requirement or the need of solving current problem using available technology.

The Design and Modeling of 30 GHz Microwave Front-End

This chapter aims to discuss a millimeter wave integrated circuit (MMWIC) in frequency of 30 GHz especially switch (SPDT), medium power amplifier (MPA) and low noise amplifier (LNA). The switch is developed using a commercial 0.15 µm GaAs pHEMT technology. It achieves low loss and high isolation for millimeter wave applications. The circuit and layout drawing of SPDT switch are done by using Advanced Design System (ADS) software. The layout is verified by running the Design Rules Check (DRC) to check and clear all the errors. At the operating frequency of 30 GHz, the reported SPDT switch has 1.470 dB insertion loss and 37.455 dB of isolation. It also demonstrates 26.00 dBm of input P1dB gain compression point (P1dB) and 22.975 dBm of output P1dB. At a supply voltage of 3.0 V and 30 GHz operating frequency, this two-stage LNA achieves an associated gain of 21.628 dB, noise figure (NF) of 2.509 dB and output referred 1-dB compression point (P1dB) of -11.0 dBm, the total power consumptions for the LNA is 174 mW. At a supply voltage of 6.0 V and 30 GHz operating frequency, a 2-stage MPA achieves a linear gain (S21) of 13.236 dB, P1dB of 22.5 dBm, power gain of 11.055 dB and the PAE of 14.606%. The total power consumption for the MPA is 1.122 W. The 30 GHz LNA and PA can be applied in direct broadcast satellite (DBS), automotive radar transmitter and receiver.

The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

LNA is an electronic amplifier that is required in receiver systems to increase the amplitude of the very low level signals from the antenna without adding too much noise. Software Advance Design System (ADS) was used to simulate the circuit and design the layout. LNA was designed using cascode topology with feedback techniques which produces better matching and unconditionally stable over the entire desired frequencies. For the 2.4 GHz operation, the amplifier achieves gain of 14.949 dB, noise figure of 1.951 dB and input reflection coefficient of -10.419 dB. With operating voltage supply at 3V, the total current consumption is 13 mA. For 3.5GHz amplifier, gain is 22.985 dB, noise figure is 1.964dB, input reflection coefficient is -12.427 dB and current consumption is 18 mA.

The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

This chapter discusses the design of MMIC power amplifiers for wireless application by using 0.15 µm GaAs Power Pseudomorphic High Electron Mobility Transistor (PHEMT) technology with a gate width of 100 µm and 10 fingers at 2.4 GHz and 3.5 GHz. The design methodology for power amplifier design can be broken down into three main sections: architecture design, small-signal design, and large-signal optimization. For 2.4 GHz power amplifier, with 3.0 V drain voltage, the amplifier has achieved 17.265 dB small-signal gain, input and output return loss of 16.310 dB and 14.418 dB, 14.862 dBm 1-dB compression power with 12.318% power-added efficiency (PAE). For 3.5GHz power amplifier, the amplifier has achieved 14.434 dB small-signal gain, input and output return loss of 12.612 dB and 11.746 dB, 14.665 dBm 1-dB compression power with 11.796% power-added efficiency (PAE). The 2.4 GHz power amplifier can be applied for Wireless LAN applications such as WiFi and WPAN whereas 3.5 GHz power amplifier for WiMax base station.

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

LNA is one very essential bloc in the RF receiver. Due to the growth of the standard evolution, this component must handle several frequency bands with the best performances. This chapter presents a wide band LNA design for IEEE802.16 standard with the CMOS 0.35µm technology. In this LNA, we use a CPW transmission line to design the inductive degeneration inductor of 0.38nH. This circuit has a S21 of 12dB, a noise figure less than 3dB and an input/output reflexion coefficient less than -10dB between 2 and 6GHz. The CPW line presents a characteristic impedance of 120O, an inductance of 0.38nH, a capacitance of few fF and a resistance less than 2O on the desired frequency band.

LNA Inventions

The main design goals of an LNA are to achieve low noise figure, high gain, good linearity and good matching and reverse isolation. The choice of the LNA topology is therefore very important to suit the design application. Five LNA topologies were studied, analyzed and compared in this chapter. The topologies are the Simultaneous Noise and Input Matching (SNIM), Power-constrained Simultaneous Noise and Input Matching (PCSNIM), Current-reuse (CR) and Folded-cascode (FC) LNAs. The last topology is the PCSNIM with buffer. The circuits are analyzed in detail in terms of their functionality and compared based on the LNAs typical performance metrics. From the analysis, the PCSNIM technique can improve matching and noise performance of the inductively degenerated cascode. The current-reuse is found to consume less current but maintaining the circuit’s transconductance to achieve the desirable gain. The folded-cascode operates at lower voltage and hence is suitable for low-powered designs. Consequently, it is also resulting in the lowest noise-figure amongst the other designs.

RF and Microwave Test of MMICs from Qualification to Mass Production

This chapter describes some basic characteristic responses that must be known for each Monolithic Microwave Integrated Circuits. The main parameters such Return Loss, Insertion Losses or Gain, Power at 1dB compression, InterModulation Products or Noise Figure are very important and have to be measured before using the device in final applications. Basic rules of Test and Measurement in RF and Microwaves, as well for characterization on benches as for high volume production using Automatic Test Equipments installed in test platforms, are summarized for helping today’s test engineers to develop their own test solutions. The device, that was characterized on bench and tested in production environment, is a monolithic, integrated low noise amplifier (LNA) and mixer usable in RF receiver Front-End applications for Personal Communications functioning on frequency wideband between 0.1 and 2.0 GHz.

Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications

This paper presents the design of single-stage and two-stage medium power amplifiers (MPAs) using GaAs PHEMT technology for the wireless applications. The single-stage MPA was designed using 0.15 µm GaAs PHEMT technology to be operated at 3.5 GHz whereas the two-stage MPA was designed using 0.5 µm GaAs PHEMT technology to be operated at 5.8 GHz. The MPAs employ a simple RC feedback in order to linearize the stages as well as to improve the circuit stability and to control the gain. In addition, the load-pull technique was used in order to define the optimum load and maximum output power. Therefore, the performance of the proposed amplifier in this paper is discussed in terms of stability, gain, power-added efficiency (PAE), and output power. The simulated data of the proposed MPAs is then compared with the measured data of the fabricated MPAs.

Optimization of CMOS Quadrature VCO Using a Graphical Method

This chapter describes the design and the optimization of Quadrature Voltage Controlled Oscillators (QVCOs) based on the coupling of two LC-tank VCO. This work covers the phase noise analysis, a graphical optimization approach, already used to optimize LC oscillator phase noise (Andreani, Bonfanti, Romano, & Samori, 2002), to optimize QVCO phase noise while satisfying design constraints such as power dissipation, tank amplitude, tuning range and start up condition. The cross-coupling transistors impact on phase noise for different configurations is especially addressed. The obtained BS-QVCO, using 0.35µm CMOS process, can be tuned between 2.2GHz and 2.58GHz, and shows a phase noise of -129 dBc/Hz at 1MHz offset from a 2.4 GHz carrier, for a current consumption of 9.25mW. The equivalent phase error and amplitude error between I and Q signals are respectively 0.65° and 1.87%.

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization by the Simulated Annealing Technique

This chapter presents the optimal design of Low Noise Amplifiers (LNAs). The basic idea consists of optimizing performances of LNAs by a direct action on the scattering parameters. A symbolic approach, namely the Coates Flow-Graph technique, is used to automatically generate symbolic expressions of the impedance parameters and, thus, those of the scattering parameters. The Simulated Annealing optimization technique is applied to determine the optimal sizing of the LNA. ADS simulation results are given to show the viability of the proposed approach.