scholarly journals A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1369
Author(s):  
Dongquan Huo ◽  
Luhong Mao ◽  
Liji Wu ◽  
Xiangmin Zhang
Keyword(s):  
Power Consumption ◽  
Flicker Noise ◽  
Analytical Formula ◽  
Direct Conversion ◽  
Low Noise ◽  
Cmos Process ◽  
Passive Mixer ◽  
Dc Offset ◽  
Front End ◽  
Rf Front End

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

CMOS EVEN HARMONIC SWITCHING MIXER FOR DIRECT CONVERSION RECEIVERS

2006 ◽  
Vol 15 (02) ◽  
pp. 183-196 ◽  
Author(s):  
J. J. LIU ◽  
M. A. DO ◽  
X. P. YU ◽  
K. S. YEO ◽  
S. JIANG ◽  
...  
Keyword(s):  
Power Consumption ◽  
Flicker Noise ◽  
Noise Figure ◽  
Direct Conversion ◽  
Cmos Process ◽  
Dc Offset ◽  
Direct Conversion Receivers ◽  
Dc Power ◽  
Mixer Design ◽  
Cmos Mixer

DC offset and high flicker noise are the main problems for the direct conversion CMOS mixer design. A novel even harmonic switching mixer implemented in a standard 0.18 μm CMOS process for applications in 2.45 GHz direct conversion receivers is proposed. The mixer circuit overcomes the problems of DC offset and high flicker noise. It achieves -8.24 dB gain, 5.2 dB DSB noise figure at 100 KHz, 17.25 dBm IIP3 and zero DC power consumption.

scholarly journals Energy Efficiency Analysis of MIMO Wideband RF Front-End Receivers

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7070
Author(s):  
Eduil Nascimento Junior ◽  
Guilherme Theis ◽  
Edson Leonardo dos Santos ◽  
André Augusto Mariano ◽  
Glauber Brante ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Noise ◽  
Low Power Consumption ◽  
Communication Link ◽  
Active Antennas ◽  
Front End ◽  
Rf Front End

Energy-efficiency is crucial for modern radio-frequency (RF) receivers dedicated to Internet of Things applications. Energy-efficiency enhancements could be achieved by lowering the power consumption of integrated circuits, using antenna diversity or even with an association of both strategies. This paper compares two wideband RF front-end architectures, based on conventional low-noise amplifiers (LNA) and low-noise transconductance amplifiers (LNTA) with N-path filters, operating with three transmission schemes: single antenna, antenna selection and singular value decomposition beamforming. Our results show that the energy-efficiency behavior varies depending on the required communication link conditions, distance between nodes and metrics from the front-end receivers. For short-range scenarios, LNA presents the best performance in terms of energy-efficiency mainly due to its very low power consumption. With the increasing of the communication distance, the very low noise figure provided by N-path LNTA-based architectures outperforms the power consumption issue, yielding higher energy-efficiency for all transmission schemes. In addition, the selected front-end architecture depends on the number of active antennas at the receiver. Hence, we can observe that low noise figure is more important with a few active antennas at the receiver, while low power consumption becomes more important when the number of active RF chains at the receiver increases.

Low Noise and Highly Linear Wideband CMOS RF Front-End for DVB-H Direct-Conversion Receiver

2012 ◽  
Vol E95.B (7) ◽  
pp. 2498-2500 ◽  
Author(s):  
Ilku NAM ◽  
Hyunwon MOON ◽  
Doo Hyung WOO
Keyword(s):  
Direct Conversion ◽  
Low Noise ◽  
Front End ◽  
Rf Front End ◽  
Cmos Rf

A Highly-Integrated Low-Noise MICS Band Receiver RF Front-End IC with AC-Coupled Current Mirror Amplifier

2018 ◽  
Vol 28 (01) ◽  
pp. 1950010 ◽  
Author(s):  
Hyouk-Kyu Cha
Keyword(s):  
Integrated Circuit ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Noise Current ◽  
Simulated Performance ◽  
Front End ◽  
Rf Front End ◽  
Mics Band ◽  
Layout Area

This work presents a low-noise, low-power receiver RF front-end integrated circuit (IC) for 402–405[Formula: see text]MHz medical implant communications service (MICS) band applications using 0.18-[Formula: see text]m CMOS process. The proposed front-end employs an AC-coupled current mirroring amplifier in between the low-noise current-reuse transconductor amplifier and a single-balanced IQ mixer for improved gain and noise performance in comparison to previous works. The designed front-end IC achieves a simulated performance of 36.5[Formula: see text]dB conversion gain, 1.85[Formula: see text]dB noise figure, and IIP3 of [Formula: see text][Formula: see text]dBm while consuming 440[Formula: see text][Formula: see text]W from 1-V voltage supply. The consumed core layout area, including I/Q LO generation and current bias circuits, is only 0.29[Formula: see text]mm2.

scholarly journals RF Transceiver for the Multi-Mode Radar Applications

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  
Keyword(s):  
Long Range ◽  
Integrated Circuit ◽  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
Doppler Frequency ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Dc Offset ◽  
Multi Mode

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

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