Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structure
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2016 ◽
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2020 ◽
Vol 64
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pp. 165-172
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Vol 136
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pp. 1555-1566
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Vol 24
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pp. 979-984
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2020 ◽
Vol 1654
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pp. 012081
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