On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation

2002 ◽  
Author(s):  
Kuen-Jong Lee ◽  
Jing-Jou Tang ◽  
Wern-Yih Duh
Keyword(s):  
Test Pattern ◽  
Fault Simulation ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Threshold Voltages

scholarly journals BIST-Based Fault Diagnosis in the Presence of Embedded Memories

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 487-500
Author(s):  
Jacob Savir
Keyword(s):  
Fault Diagnosis ◽  
Efficient Method ◽  
Test Pattern ◽  
Fault Simulation ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Diagnostic Problem ◽  
Memory Control ◽  
Embedded Memories

An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.

Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits

2015 ◽  
Author(s):  
Kuan-Ying Chiang ◽  
Yu-Hao Ho ◽  
Yo-Wei Chen ◽  
Cheng-Sheng Pan ◽  
James Chien-Mo Li
Keyword(s):  
Test Pattern ◽  
Fault Simulation ◽  
Pattern Generation ◽  
Test Pattern Generation
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