PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment

2008 ◽  
Author(s):  
Yi-Tsung Lin ◽  
Meng-Fan Wu ◽  
Jiun-Lang Huang
Keyword(s):  
Power Supply ◽  
Test Pattern ◽  
Pattern Generation ◽  
Huffman Coding ◽  
Test Pattern Generation ◽  
Scan Testing ◽  
Test Compression ◽  
Generation Technique ◽  
Supply Noise ◽  
Noise Test

A Test Pattern Generation Technique for Approximate Circuits Based on an ILP-Formulated Pattern Selection Procedure

2019 ◽  
Vol 18 ◽  
pp. 849-857 ◽  
Author(s):  
Marcello Traiola ◽  
Arnaud Virazel ◽  
Patrick Girard ◽  
Mario Barbareschi ◽  
Alberto Bosio
Keyword(s):  
Test Pattern ◽  
Selection Procedure ◽  
Pattern Generation ◽  
Pattern Selection ◽  
Test Pattern Generation ◽  
Generation Technique

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

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