A High-Speed Low-Power Rail-to-Rail Buffer Amplifier for LCD Application

2006 ◽  
Author(s):  
Chih-wen Lu ◽  
Peter H. Xiao
Keyword(s):  
Low Power ◽  
High Speed ◽  
Rail To Rail ◽  
Buffer Amplifier

A COMPACT HIGH-SPEED LOW-POWER RAIL-TO-RAIL BUFFER AMPLIFIER FOR STEP-PULSE SIGNALS

2010 ◽  
Vol 19 (06) ◽  
pp. 1181-1197 ◽  
Author(s):  
CHIH-WEN LU ◽  
CHING-MIN HSIAO
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Feedback Loops ◽  
Common Source ◽  
Experimental Prototype ◽  
Rail To Rail ◽  
Buffer Amplifier ◽  
Voltage Swing

A compact high-speed low-power rail-to-rail buffer amplifier, which is suitable for driving heavy capacitive loads, is proposed. The buffer amplifier is composed of a pair of push-pull output transistors with two feedback loops consisting of a pair of complementary error amplifiers and a pair of complementary common-source amplifiers. The buffer draws little current while static but has a large driving capability while transient. A mutual bias scheme is also proposed to reduce the power consumption and the die area for LCD applications. An experimental prototype buffer amplifier implemented in a 0.35 μm CMOS technology demonstrates that the settling time is 1.5 μs for a voltage swing of 0.1 ~ (VDD–0.1) V under a 600 pF capacitance load. Quiescent current of 4 μA is measured. The area of this buffer is 32 × 109 μm2.

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

IMPROVED LOW-POWER HIGH-SPEED BUFFER AMPLIFIER WITH SLEW-RATE ENHANCEMENT FOR LCD APPLICATIONS

2010 ◽  
Vol 19 (02) ◽  
pp. 325-334 ◽  
Author(s):  
DAVIDE MARANO ◽  
GAETANO PALUMBO ◽  
SALVATORE PENNISI
Keyword(s):  
Low Power ◽  
High Speed ◽  
Liquid Crystal Display ◽  
Slew Rate ◽  
Output Stage ◽  
Line Load ◽  
Rate Enhancement ◽  
Static Operation ◽  
Limited Power ◽  
Buffer Amplifier

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply.

A RAIL-TO-RAIL BUFFER AMPLIFIER FOR LCD DRIVER

2011 ◽  
Vol 20 (07) ◽  
pp. 1377-1387 ◽  
Author(s):  
CHIH-WEN LU ◽  
CHING-MIN HSIAO
Keyword(s):  
High Speed ◽  
Liquid Crystal Display ◽  
Stable State ◽  
Cmos Technology ◽  
Offset Voltage ◽  
Rail To Rail ◽  
Lcd Driver ◽  
Display Driver ◽  
Buffer Amplifier ◽  
Voltage Swing

A high-speed low-power rail-to-rail buffer amplifier, which is suitable for liquid crystal display driver applications, is proposed. An offset voltage is intentionally built in the second stage to cut off the transistors of last stage from the output node in the stable state and hence achieve low dc power consumption. The input referred offset voltage due to the built-in offset is very small. The buffer draws little current while static but has a large driving capability while transient. An experimental prototype buffer amplifier implemented in a 0.35-μm CMOS technology demonstrates that the circuit can operate under a wide power supply range. Quiescent current of 5 μA is measured. The buffer exhibits the settling time of 1.5 μs for a voltage swing of 0.1 ~ (VDD – 0.1) V under a 600 pF capacitance load. The area of this buffer is 30 × 98 μm2. The measured data show that the proposed output buffer amplifier is very suitable for LCD driver applications.

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