A fully differential 1.5 V low-power CMOS operational amplifier with a rail-to-rail current-regulated constant-g/sub m/ input stage

Author(s):  
E. Peeters ◽  
M. Steyaert ◽  
W. Sansen
2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.


2017 ◽  
Vol 13 (1) ◽  
pp. 67-75 ◽  
Author(s):  
P. Karuppanan ◽  
Soumya Ranjan Ghosh ◽  
Kamran Khan ◽  
Pavan Kumar Bikki

2013 ◽  
Vol 60 (9) ◽  
pp. 2333-2342 ◽  
Author(s):  
Cristina Azcona ◽  
Belen Calvo ◽  
Santiago Celma ◽  
Nicolas Medrano ◽  
Pedro A. Martinez

2014 ◽  
Vol 979 ◽  
pp. 62-65
Author(s):  
Thawatchai Thongleam ◽  
Varakorn Kasemsuwan

In this paper, a feedforward bulk-driven class AB fully-differential second-generation current conveyer (FDCCII) is presented. Bulk-driven differential pair is employed for the input stage allowing the FDCCII to operate with rail-to-rail operation. Feedfoward technique is also incorporated into input stage to increase the DC gain and minimize the common mode gain. The circuit performance is verified using HSPICE in 0.18 μm CMOS technology. The simulation results show rail-to-rail input and output swings. The DC voltage transfer characteristic between ports Y and X and DC current transfer characteristic between ports X and Z shows good linearity. The bandwidths show 25.7 MHz (VX/VY), 30 MHz (IZ/IX), respectively. The power dissipation is 267.5 μW.


2012 ◽  
Vol 43 (1) ◽  
pp. 69-76 ◽  
Author(s):  
Tamer Farouk ◽  
Ahmed Nader Mohieldin ◽  
Ahmed Hussien Khalil

Sign in / Sign up

Export Citation Format

Share Document