Design considerations for a hybrid fiber coax high-speed data access network

Author(s):  
D. Picker
2012 ◽  
Vol 182-183 ◽  
pp. 706-710 ◽  
Author(s):  
Cheng Jun Zhang ◽  
Xiao Yan Zuo ◽  
Chi Zhang ◽  
Xiao Guang Wu

Through analyzing the pattern data of computerized jacquard knitting wrap machine, comparing the current storages structure and type, this paper introduces a method for Flash file structure of jacquard data. The method takes advantage of ARM chip to achieve the operations for access and modification of Flash, designing a management procedures of jacquard data access from the perspective of increasing the Flash life. The management procedures not only complete read and write operations, but also meet the requirement of jacquard high-speed data transfer.


Author(s):  
Tawhid Kawser ◽  
MOHAMMED R. AL-AMIN ◽  
KHONDOKER Z. ISLAM ◽  
SIFAT-E- MOHAMMAD

Mobile WiMAX is expected to be the next generation radio-interface, complementing WLAN and challenging EVDO/HSPA/LTE. High speed data rate, reduced latency, better Quality of service, and mobility can allow WiMAX to meet the rapidly growing demand of the users. A study of WiMAX Radio Network Planning (RNP) for an urban area like Dhaka city in Bangladesh is presented in this paper in order to help predetermine the radio access infrastructure requirements. A suitable radio planning tool has been used for this purpose. The simulation results of throughput and Carrier to Interference plus Noise Ratio (CINR) are provided.


2014 ◽  
Vol 912-914 ◽  
pp. 1556-1560
Author(s):  
Sheng Kun Li ◽  
Cheng Qun Chu ◽  
Hai Liang Chen ◽  
Fang Ma

The large-capacity, high-speed and low power consumption become the new requirements for the data storage systems. In this paper, a high-performance storage module based on multiple NAND flash memory chips is presented to real-time massive data acquisition system. In order to achieve the miniaturization dimension and the high-speed data storage design requirements, the paper presents a small size and high-speed storage unit based on NAND flash, where the dimensions of the module can reach 33mm×33mm and the maximum rate is up to 60MB/s. Ensuring continuous and reliable operation requires a dedicated buffering for the data transmission. We analyze the elements and peculiarities of the flash memory chip and propose a multi-way architecture to speed up data access. The design of a multilevel high-speed buffer structure based on the field programmable gate array (FPGA) technology is introduced in the paper. The proposed system can be applicable to some portable digital equipment.


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