ADC architectures and technology

2005 ◽  
Author(s):  
M. Snelgrove
Keyword(s):  
Adc Architectures

Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices

2016 ◽  
pp. 199-228 ◽  
Author(s):  
Nabi Sertac Artan
Keyword(s):  
Low Power ◽  
Medical Devices ◽  
Sar Adc ◽  
The Other ◽  
Implantable Medical Devices ◽  
Ultra Low Power ◽  
Analog To Digital ◽  
Electrophysiological Signals ◽  
Recent Developments ◽  
Adc Architectures

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.

Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

2008 ◽  
Vol 55 (6) ◽  
pp. 1441-1454 ◽  
Author(s):  
P. Nuzzo ◽  
F. De Bernardinis ◽  
P. Terreni ◽  
G. Van der Plas
Keyword(s):  
Noise Analysis ◽  
Adc Architectures

CFCS calibration circuit design for multi-bit pipelined ADC architectures

2018 ◽  
Vol 24 (12) ◽  
pp. 4825-4831
Author(s):  
Hari Shanker Gupta ◽  
Satyajit Mohapatra ◽  
Nisha Pandya ◽  
Nihar Mohapatra ◽  
Rohit Vasoliya ◽  
...  
Keyword(s):  
Circuit Design ◽  
Pipelined Adc ◽  
Adc Architectures

Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices

2018 ◽  
pp. 413-443
Author(s):  
Nabi Sertac Artan
Keyword(s):  
Low Power ◽  
Medical Devices ◽  
Sar Adc ◽  
The Other ◽  
Implantable Medical Devices ◽  
Ultra Low Power ◽  
Analog To Digital ◽  
Electrophysiological Signals ◽  
Recent Developments ◽  
Adc Architectures

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.

scholarly journals Noise shaping in SAR ADC

2020 ◽  
Vol 33 (1) ◽  
pp. 15-26
Author(s):  
Dmitry Osipov ◽  
Aleksandr Gusev ◽  
Vitaly Shumikhin ◽  
Steffen Paul
Keyword(s):  
Power Efficiency ◽  
Sampling Rate ◽  
Complementary Metal Oxide Semiconductor ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Noise Shaping ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Noise Transfer Function ◽  
Adc Architectures

The successive approximation register (SAR) analog-to-digital converter (ADC) is currently the most popular type of ADC architecture, owing to its power efficiency. They are also used in multichannel systems, where power efficiency is of high importance because of the large number of simultaneously working channels. However, the SAR ADC architecture is not the most area efficient. In SAR ADCs, the binary weighted capacitive digital-to-analog converter (DAC) is used, which means that one additional bit of resolution costs double the increase of area. Oversampling and noise shaping are methods that allow an increase in resolution without an increase of area. In this paper we present the new SAR ADC architectures with a noise shaping. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. We propose two modifications of the architecture: with zero-only NTF and with the NTF with additional pole. The additional pole theoretically increases the efficiency of noise shaping to further 3 dB. The architectures were applied to the design of SAR ADCs in a 65 nm complementary metal-oxide semiconductor (CMOS) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architectures provide nearly 4 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.

MONOTONIC ERROR ELIMINATION IN SUBRANGE A/D CONVERTERS

2013 ◽  
Vol 22 (01) ◽  
pp. 1250073
Author(s):  
N. PETRELLIS ◽  
G. ADAM ◽  
D. VENTZAS
Keyword(s):  
Processing Method ◽  
Post Processing ◽  
Signal To Noise ◽  
Successful Operation ◽  
Elimination Method ◽  
Processing Methods ◽  
Error Elimination ◽  
Simulation Results ◽  
Adc Architectures ◽  
Oversampling Ratio

Monotonic errors cause severe errors and are inherent in several A/D Converter (ADC) architectures. Moreover, several error correcting and ADC output processing methods require a monotonic behavior for a successful operation. Based on the features of asynchronous ADCs, an architecture for the elimination of monotonic errors is presented. This monotonic error correcting module is connected at the output of an ADC and does not require any modification in its internal circuits. It controls an output buffering stage that discards output codes with monotonic errors and this correcting procedure is triggered by changes in specific output bits of the ADC. Simulation results show an improvement by 8 dB or 25% maximum, in the signal-to-noise and distortion ratio (SNDR) of an 8-bit ADC if this monotonic error elimination method is used alone and a further improvement by 1–5 dB if it is combined with a post processing method developed by the authors. Similar improvement can also be achieved in several other architectures like Subrange or Folding ADCs that operate in relatively high oversampling ratio and suffer from monotonic errors with specific features.

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