Systematic software-based self-test for pipelined processors

2006 ◽  
Author(s):  
M. Psarakis ◽  
D. Gizopoulos ◽  
M. Hatzimihail ◽  
A. Paschalis ◽  
A. Raghunathan ◽  
...  
Keyword(s):  
Self Test ◽  
Pipelined Processors

Systematic Software-Based Self-Test for Pipelined Processors

2008 ◽  
Vol 16 (11) ◽  
pp. 1441-1453 ◽  
Author(s):  
D. Gizopoulos ◽  
M. Psarakis ◽  
M. Hatzimihail ◽  
M. Maniatakos ◽  
A. Paschalis ◽  
...  
Keyword(s):  
Self Test ◽  
Pipelined Processors

Software-based self-test for pipelined processors: a case study

2006 ◽  
Author(s):  
M. Hatzimihail ◽  
G. Xenoulis ◽  
M. Psarakis ◽  
D. Gizopoulos ◽  
A. Paschalis
Keyword(s):  
Self Test ◽  
Pipelined Processors

scholarly journals Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

2021 ◽  
Author(s):  
Riccardo Cantoro ◽  
Patrick Girard ◽  
Riccardo Masante ◽  
Sandro Sartoni ◽  
Matteo Sonza Reorda ◽  
...  
Keyword(s):  
Fault Coverage ◽  
Transition Fault ◽  
Self Test ◽  
Pipelined Processors

Systematic software-based self-test for pipelined processors

2006 ◽  
Author(s):  
Mihalis Psarakis ◽  
Dimitris Gizopoulos ◽  
Miltiadis Hatzimihail ◽  
Antonis Paschalis ◽  
Anand Raghunathan ◽  
...  
Keyword(s):  
Self Test ◽  
Pipelined Processors

The Audit Self Test

2013 ◽  
Keyword(s):  
Self Test

Memory Implementation in a System on Chip with Built-in Self-Test and Recovery Tools

2019 ◽  
Vol 24 (3) ◽  
pp. 239-247
Author(s):  
Vladimir G. Ryabtsev ◽  
◽  
Sergey V. Volobuev ◽  
Keyword(s):  
System On Chip ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
Recovery Tools

RF Phase Error Built-In-Self-Test for A GSM SOC

2008 ◽  
Vol 1 (4) ◽  
pp. 39-44
Author(s):  
Dallas Webster ◽  
Loi Phan ◽  
Oren Eliezer ◽  
Rick Hudgens ◽  
Donald Lie
Keyword(s):  
Phase Error ◽  
Self Test ◽  
Built In Self Test

Laser Silicon Interaction Study on Ring Oscillators to Establish Temperature Voltage Dependency Trends on 14 nm and Future FinFET Technologies

2017 ◽  
Author(s):  
Gaurav Mattey ◽  
Lava Ranganathan
Keyword(s):  
High Speed ◽  
Laser Frequency ◽  
Ring Oscillator ◽  
Switching Speed ◽  
Dual Nature ◽  
Voltage Imaging ◽  
Multiple Cores ◽  
Speed Performance ◽  
Self Test ◽  
Frequency Changes

Abstract Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.

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