Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level

Author(s):  
Hassan Ebrahimi ◽  
Hans G. Kerkhoff
2015 ◽  
Vol 25 (03) ◽  
pp. 1640014
Author(s):  
Florence Azaïs ◽  
Stéphane David-Grignot ◽  
Laurent Latorre ◽  
François Lefevre

This paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140[Formula: see text]nm technology occupies only 7,885[Formula: see text][Formula: see text]m2, which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument.


Author(s):  
Weihai Sun ◽  
Lemei Han

Machine fault detection has great practical significance. Compared with the detection method that requires external sensors, the detection of machine fault by sound signal does not need to destroy its structure. The current popular audio-based fault detection often needs a lot of learning data and complex learning process, and needs the support of known fault database. The fault detection method based on audio proposed in this paper only needs to ensure that the machine works normally in the first second. Through the correlation coefficient calculation, energy analysis, EMD and other methods to carry out time-frequency analysis of the subsequent collected sound signals, we can detect whether the machine has fault.


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