Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits
2015 ◽
Vol 25
(03)
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pp. 1640014
Keyword(s):
On Chip
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This paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140[Formula: see text]nm technology occupies only 7,885[Formula: see text][Formula: see text]m2, which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument.
Keyword(s):
Keyword(s):
2016 ◽
Vol 8
(4)
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pp. 81-91
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