A Low Power Biopotential Amplifier based on Bulk Driven Quasi Floating Gate Technique

2019 ◽  
Author(s):  
Preeti Sharma ◽  
Kulbhushan Sharma ◽  
H. S. Jatana ◽  
Rajnish Sharma
Keyword(s):  
Low Power ◽  
Floating Gate ◽  
Biopotential Amplifier

A 0.09 $\mu$ W Low Power Front-End Biopotential Amplifier for Biosignal Recording

2012 ◽  
Vol 6 (5) ◽  
pp. 508-516 ◽  
Author(s):  
Yuhwai Tseng ◽  
Yingchieh Ho ◽  
Shuoting Kao ◽  
Chauchin Su
Keyword(s):  
Low Power ◽  
Front End ◽  
Biopotential Amplifier

A Novel Dual-Doping Floating-Gate (DDFG) Flash Memory Featuring Low Power and High Reliability Application

2007 ◽  
Vol 28 (7) ◽  
pp. 622-624 ◽  
Author(s):  
Yan Li ◽  
Ru Huang ◽  
Yimao Cai ◽  
Falong Zhou ◽  
Xiaonan Shan ◽  
...  
Keyword(s):  
Low Power ◽  
Flash Memory ◽  
High Reliability ◽  
Floating Gate

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

2016 ◽  
Vol 4 (2) ◽  
pp. 333 ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Stability ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Power Supply Voltage ◽  
Operation Analysis ◽  
Sram Cell ◽  
Simulation Results

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>

Sign in / Sign up

Export Citation Format

Share Document