Development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width

Author(s):  
A. Ruangphanit ◽  
A. Poyai ◽  
R. Muanghlua ◽  
S. Niemcharoen ◽  
W. Titiroongruang
2014 ◽  
Vol 931-932 ◽  
pp. 984-988
Author(s):  
Anucha Ruangphanit ◽  
Natthaphon Sakuna ◽  
Surasak Niemcharoen ◽  
Rangson Muanghlua

Author(s):  
Kiran Agarwal Gupta ◽  
V Venkateswarlu ◽  
Dinesh Anvekar ◽  
Sumit Basu

1976 ◽  
Vol 19 (1) ◽  
pp. 77-81 ◽  
Author(s):  
Karl E. Kroell ◽  
Gerhard K. Ackermann

2011 ◽  
Vol 32 (6) ◽  
pp. 791-793 ◽  
Author(s):  
Stefano Poli ◽  
Susanna Reggiani ◽  
Marie Denison ◽  
Elena Gnani ◽  
Antonio Gnudi ◽  
...  

2010 ◽  
Vol 645-648 ◽  
pp. 961-964 ◽  
Author(s):  
Jang Kwon Lim ◽  
Mietek Bakowski ◽  
Hans Peter Nee

The 1.2 kV 4H-SiC buried-grid vertical JFET structures with Normally-on (N-on) and Normally-off (N-off) design were investigated by simulations. The conduction and switching properties were determined in the temperature range from -50°C to 250°C. In this paper, the characteristics of the N-on designs with threshold voltage (Vth) of -50 V and -10 V are compared with the N-off design (Vth=0). The presented data are for devices with the same channel length at 250°C. The results show that the on-resistance (Ron) decreases with increasing channel doping concentration and decreasing channel width. The presented turn-on, Eon, and turn-off, Eoff, energies per pulse are calculated under the switching conditions 100 A/cm2 and 600 V with a gate resistance of Rg=1 . For the two N-on designs the total switching losses, Esw=Eon+Eoff, differ less than 30% with Wch 0.7 m. With Wch=0.5 m the switching losses of N-off design are almost one order of magnitude higher than those of the N-on design with Vth = -50 V.


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