This paper presents the physical level design analysis of 3D stacked memory ICs with Through Silicon Via (TSV) to compute the propagation delay. The difficulties in incorporating TSVs for 3D ICs are that TSV has additional complex parasitics, process based variations, and structure based reliability issues, thus warranting detailed modeling and analysis. TSVs are known to have a MOS structure which has been rigorously studied to evaluate the overall TSV performance and the effect of variable wafer doping profiles has been included in our analysis. Our proposed TSV model provides the IC designer with the yardstick for optimum TSV pitch. Furthermore, our model considers the TSVs to have a variable capacitor which enables frequency selective characteristics based on signal strength and operating frequency. Finally, we have incorporated our model towards optimization of memory array size in 3D stacked DRAMs while taking into account the key factors of TSV delay for a given process node and TSV pitch. This exhaustive analysis would help to choose optimum memory array size while stacking, without degradation in overall 3D Dynamic Random Access Memory (DRAM) performance, and can be effectively used as a primary guideline during memory stacking and layout for optimum bandwidth.
Cost Modeling and Analysis of TSV and Contactless 3D-ICs