A low phase noise 10 GHz VCO in 0.18/spl mu/m CMOS process

2005 ◽  
Author(s):  
Tae-young Choi ◽  
Hanil Lee ◽  
L.P.B. Katehi ◽  
S. Mohammadi
Keyword(s):  
Phase Noise ◽  
Cmos Process ◽  
Low Phase Noise

A Low Phase Noise $LC$ VCO in 65 nm CMOS Process Using Rectangular Switching Technique

2007 ◽  
Vol 17 (8) ◽  
pp. 610-612 ◽  
Author(s):  
Huijung Kim ◽  
Woonyun Kim ◽  
Seonghan Ryu ◽  
Sanghoon Kang ◽  
Byeong-Ha Park ◽  
...  
Keyword(s):  
Phase Noise ◽  
Cmos Process ◽  
Low Phase Noise ◽  
Lc Vco

A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process

2012 ◽  
Vol 33 (7) ◽  
pp. 075004 ◽  
Author(s):  
Haijun Gao ◽  
Lingling Sun ◽  
Xiaofei Kuang ◽  
Liheng Lou
Keyword(s):  
Phase Noise ◽  
Fine Tuning ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Low Phase Noise

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

scholarly journals A Very Low-phase-noise CMOS Ring VCO Intended for Sensor Interfaces

2021 ◽  
Author(s):  
Mahin Esmaeilzadeh ◽  
Yves Audet ◽  
Mohamed Ali ◽  
Mohamad Sawan
Keyword(s):  
Phase Noise ◽  
Tuning Range ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Silicon Area ◽  
Wide Range ◽  
Extended Frequency ◽  
Sensor Interfaces ◽  
Low Phase Noise ◽  
Analytical Expressions

<p>We describe in the paper a ring voltage-controlled oscillator (VCO) indicating an improved phase noise over a wide range of frequency offsets and an extended frequency/voltage tuning range. The phase noise is improved by leveraging a better linearity approach, while reducing the VCO gain and maintaining wide tuning range. The proposed VCO is a block of a time-domain comparator embedded in a monitoring and readout circuit of an industrial sensor interface. An analytical model is extracted resulting in closed-form expressions for both input-referred noise and phase noise of the VCO. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The prototype of the proposed VCO was implemented and fabricated in a 0.35 µm CMOS process. The integrated VCO consumes 0.903 mW from a 3.3 V supply, when running at its maximum frequency of 9.37 MHz. The measured phase noise of the proposed VCO is -147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the occupied silicon area of circuit is 0.005 mm<sup>2</sup>.</p>

scholarly journals A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 935 ◽  
Author(s):  
Arash Hejazi ◽  
YoungGun Pu ◽  
Kang-Yoon Lee
Keyword(s):  
Phase Noise ◽  
Carrier Frequency ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Voltage Controlled Oscillator ◽  
Wide Range ◽  
Layout Area ◽  
Low Phase Noise

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

A 400 μW Near-Threshold Feedback Class-C VCO with Auto Amplitude Control

2018 ◽  
Vol 27 (05) ◽  
pp. 1850072
Author(s):  
Chenggang Yan ◽  
Chen Hu
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Feedback Loop ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Amplitude Control ◽  
Ultra Low Power ◽  
Class C ◽  
Low Phase Noise ◽  
Near Threshold

A 400[Formula: see text][Formula: see text]W near-threshold supply class-C voltage controlled oscillator (VCO) with amplitude feedback loop and auto amplitude control (AAC) is proposed in this paper. The amplitude feedback loop and AAC ensure the robust startup of the proposed VCO and automatically adapts it to the class-C mode in steady state. Consequently, ultra-low power can be achieved in AAC mode and low phase noise, high swing can be achieved in AAC off mode. The proposed VCO with AAC gets ultra-low power consumption by limiting the oscillating amplitude and driving the proposed VCO into the deep Class-C mode. Additionally, the peak value detector is employed in this work to boost the controlling voltage of capacitors bank. Thus, a low on resistance of switch transistors is obtained, which increases the Q value of capacitors bank. The simulated phase noise is [Formula: see text]124.5[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset with the 1.16[Formula: see text]GHz oscillation frequency. In this case, the figure-of-merit including tuning range (FOMT) of proposed VCO is [Formula: see text]195[Formula: see text]dBc/Hz. The proposed VCO is fabricated in SMIC 40[Formula: see text]nm CMOS process and consumes 0.62[Formula: see text]mA from 0.65[Formula: see text]V supply. The measured phase noise is [Formula: see text]109[Formula: see text]dBc/Hz and FOMT is [Formula: see text]179[Formula: see text]dBc/Hz.

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