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Logic systems for path delay test generation
Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference
◽
10.1109/eurdac.1993.410638
◽
2002
◽
Cited By ~ 14
Author(s):
S. Bose
◽
P. Agrawal
◽
V.D. Agrawal
Keyword(s):
Test Generation
◽
Path Delay
◽
Delay Test
◽
Logic Systems
◽
Path Delay Test
Download Full-text
Related Documents
Cited By
References
Deriving logic systems for path delay test generation
IEEE Transactions on Computers
◽
10.1109/12.707585
◽
1998
◽
Vol 47
(8)
◽
pp. 829-846
◽
Cited By ~ 8
Author(s):
S. Bose
◽
P. Agrawal
◽
V.D. Agrawal
Keyword(s):
Test Generation
◽
Path Delay
◽
Delay Test
◽
Logic Systems
◽
Path Delay Test
Download Full-text
Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation
2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems
◽
10.1109/vlsid.2014.16
◽
2014
◽
Cited By ~ 1
Author(s):
Kun Bian
◽
D.M.H. Walker
◽
Sunil P. Khatri
Keyword(s):
Test Generation
◽
Path Delay
◽
Delay Test
◽
Path Delay Test
Download Full-text
Multiple Coupling Effects Oriented Path Delay Test Generation
26th IEEE VLSI Test Symposium (vts 2008)
◽
10.1109/vts.2008.9
◽
2008
◽
Cited By ~ 2
Author(s):
Minjin Zhang
◽
Huawei Li
◽
Xiaowei Li
Keyword(s):
Test Generation
◽
Path Delay
◽
Delay Test
◽
Coupling Effects
◽
Oriented Path
◽
Path Delay Test
Download Full-text
Efficient Path Delay Test Generation for Custom Designs
ETRI Journal
◽
10.4218/etrij.01.0101.0306
◽
2001
◽
Vol 23
(3)
◽
pp. 138-150
◽
Cited By ~ 4
Author(s):
Sungho Kang Kang
◽
Bill Underwood Underwood
◽
Wai-On Law Law
◽
Haluk Konuk Konuk
Keyword(s):
Test Generation
◽
Path Delay
◽
Delay Test
◽
Path Delay Test
Download Full-text
Exploiting path delay test generation to develop better TDF tests for small delay defects
2017 IEEE International Test Conference (ITC)
◽
10.1109/test.2017.8242072
◽
2017
◽
Cited By ~ 3
Author(s):
Ankush Srivastava
◽
Adit D Singh
◽
Virendra Singh
◽
Kewal K Saluja
Keyword(s):
Test Generation
◽
Path Delay
◽
Delay Test
◽
Small Delay Defects
◽
Small Delay
◽
Delay Defects
◽
Path Delay Test
Download Full-text
Path delay test generation at functional level
IET Computers & Digital Techniques
◽
10.1049/iet-cdt.2013.0096
◽
2015
◽
Vol 9
(3)
◽
pp. 135-141
◽
Cited By ~ 1
Author(s):
Eduardas Bareisa
◽
Vacius Jusas
◽
Kestutis Motiejunas
◽
Rimantas Seinauskas
Keyword(s):
Test Generation
◽
Path Delay
◽
Delay Test
◽
Functional Level
◽
Path Delay Test
Download Full-text
Sequential logic path delay test generation by symbolic analysis
Proceedings of the Fourth Asian Test Symposium
◽
10.1109/ats.1995.485360
◽
2002
◽
Cited By ~ 6
Author(s):
S. Bose
◽
V.D. Agrawal
Keyword(s):
Test Generation
◽
Symbolic Analysis
◽
Path Delay
◽
Delay Test
◽
Sequential Logic
◽
Path Delay Test
Download Full-text
Efficient path delay test generation based on stuck-at test generation using checker circuitry
2007 IEEE/ACM International Conference on Computer-Aided Design
◽
10.1109/iccad.2007.4397301
◽
2007
◽
Author(s):
Tsuyoshi Iwagaki
◽
Satoshi Ohtake
◽
Mineo Kaneko
◽
Hideo Fujiwara
Keyword(s):
Test Generation
◽
Path Delay
◽
Delay Test
◽
Path Delay Test
Download Full-text
Mixed structural-functional path delay test generation and compaction
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
◽
10.1109/dft.2013.6653575
◽
2013
◽
Cited By ~ 5
Author(s):
Kun Bian
◽
D. M. H. Walker
◽
Sunil P. Khatri
◽
Shayak Lahiri
Keyword(s):
Test Generation
◽
Path Delay
◽
Delay Test
◽
Path Delay Test
Download Full-text
Path Delay Test Generation Toward Activation of Worst Case Coupling Effects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2010.2075945
◽
2011
◽
Vol 19
(11)
◽
pp. 1969-1982
◽
Cited By ~ 8
Author(s):
Minjin Zhang
◽
Huawei Li
◽
Xiaowei Li
Keyword(s):
Test Generation
◽
Path Delay
◽
Delay Test
◽
Coupling Effects
◽
Worst Case
◽
Path Delay Test
Download Full-text
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