path delay test Recently Published Documents

Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle

2019 IEEE 37th VLSI Test Symposium (VTS) ◽

10.1109/vts.2019.8758651 ◽

2019 ◽

Author(s):

Ben Niewenhuis ◽

Balaji Ravikumar ◽

Zeye Liu ◽

R. D. Shawn Blanton

Keyword(s):

Path Delay ◽

Delay Test ◽

Exploiting path delay test generation to develop better TDF tests for small delay defects

2017 IEEE International Test Conference (ITC) ◽

10.1109/test.2017.8242072 ◽

2017 ◽

Cited By ~ 3

Author(s):

Ankush Srivastava ◽

Adit D Singh ◽

Virendra Singh ◽

Kewal K Saluja

Keyword(s):

Test Generation ◽

Path Delay ◽

Delay Test ◽

Small Delay Defects ◽

Small Delay ◽

Delay Defects ◽

2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) ◽

Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra

10.1109/vlsid.2017.63 ◽

2017 ◽

Author(s):

Prasenjit Biswas ◽

D. M. H. Walker

Keyword(s):

Path Delay ◽

Delay Test ◽

Extended Value ◽

Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2014.2352937 ◽

2015 ◽

Vol 23 (9) ◽

pp. 1577-1590 ◽

Author(s):

Bao Liu ◽

Lu Wang

Keyword(s):

Test Pattern ◽

Timing Analysis ◽

Pattern Generation ◽

Test Pattern Generation ◽

Path Delay ◽

Delay Test ◽

Statistical Timing Analysis ◽

Statistical Timing ◽

At-Speed Path Delay Test

2015 IEEE 24th North Atlantic Test Workshop ◽

10.1109/natw.2015.13 ◽

2015 ◽

Author(s):

Swati Chakraborty ◽

D.M.H. Walker

Keyword(s):

Path Delay ◽

Delay Test ◽

Path delay test generation at functional level

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2013.0096 ◽

2015 ◽

Vol 9 (3) ◽

pp. 135-141 ◽

Author(s):

Eduardas Bareisa ◽

Vacius Jusas ◽

Kestutis Motiejunas ◽

Rimantas Seinauskas

Keyword(s):

Test Generation ◽

Path Delay ◽

Delay Test ◽

Functional Level ◽

Pseudo Functional Path Delay Test through Embedded Memories

Journal of Electronic Testing ◽

10.1007/s10836-014-5497-x ◽

2014 ◽

Vol 31 (1) ◽

pp. 35-42

Author(s):

Yukun Gao ◽

Tengteng Zhang ◽

Punj Pokharel ◽

Swati Chakraborty ◽

D. M. H. Walker

Keyword(s):

Path Delay ◽

Delay Test ◽

Embedded Memories ◽

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce

10.1109/ddecs.2014.6868791 ◽

2014 ◽

Cited By ~ 3

Author(s):

A. Asokan ◽

A. Todri-Sanial ◽

A. Bosio ◽

L. Dilillo ◽

P. Girard ◽

...

Keyword(s):

Power Supply ◽

Path Delay ◽

Power Supply Noise ◽

Delay Test ◽

Supply Noise ◽

Ground Bounce ◽

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems ◽

Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation

10.1109/vlsid.2014.16 ◽

2014 ◽

Author(s):

Kun Bian ◽

D.M.H. Walker ◽

Sunil P. Khatri

Keyword(s):

Test Generation ◽

Path Delay ◽

Delay Test ◽