Path Delay Test Generation Toward Activation of Worst Case Coupling Effects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2010.2075945 ◽

2011 ◽

Vol 19 (11) ◽

pp. 1969-1982 ◽

Author(s):

Minjin Zhang ◽

Huawei Li ◽

Xiaowei Li

Keyword(s):

Test Generation ◽

Coupling Effects ◽

Path Delay Test

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Multiple Coupling Effects Oriented Path Delay Test Generation

26th IEEE VLSI Test Symposium (vts 2008) ◽

10.1109/vts.2008.9 ◽

2008 ◽

Author(s):

Minjin Zhang ◽

Huawei Li ◽

Xiaowei Li

Keyword(s):

Test Generation ◽

Coupling Effects ◽

Oriented Path ◽

Path Delay Test

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Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems ◽

10.1109/vlsid.2014.16 ◽

2014 ◽

Author(s):

Kun Bian ◽

D.M.H. Walker ◽

Sunil P. Khatri

Keyword(s):

Test Generation ◽

Path Delay Test

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Efficient Path Delay Test Generation for Custom Designs

ETRI Journal ◽

10.4218/etrij.01.0101.0306 ◽

2001 ◽

Vol 23 (3) ◽

pp. 138-150 ◽

Author(s):

Sungho Kang Kang ◽

Bill Underwood Underwood ◽

Wai-On Law Law ◽

Haluk Konuk Konuk

Keyword(s):

Test Generation ◽

Path Delay Test

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Deriving logic systems for path delay test generation

IEEE Transactions on Computers ◽

10.1109/12.707585 ◽

1998 ◽

Vol 47 (8) ◽

pp. 829-846 ◽

Author(s):

S. Bose ◽

P. Agrawal ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Logic Systems ◽

Path Delay Test

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Exploiting path delay test generation to develop better TDF tests for small delay defects

2017 IEEE International Test Conference (ITC) ◽

10.1109/test.2017.8242072 ◽

2017 ◽

Author(s):

Ankush Srivastava ◽

Adit D Singh ◽

Virendra Singh ◽

Kewal K Saluja

Keyword(s):

Test Generation ◽

Small Delay Defects ◽

Small Delay ◽

Delay Defects ◽

Path Delay Test

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Path delay test generation at functional level

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2013.0096 ◽

2015 ◽

Vol 9 (3) ◽

pp. 135-141 ◽

Author(s):

Eduardas Bareisa ◽

Vacius Jusas ◽

Kestutis Motiejunas ◽

Rimantas Seinauskas

Keyword(s):

Test Generation ◽

Functional Level ◽

Path Delay Test

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Sequential logic path delay test generation by symbolic analysis

Proceedings of the Fourth Asian Test Symposium ◽

10.1109/ats.1995.485360 ◽

2002 ◽

Author(s):

S. Bose ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Symbolic Analysis ◽

Sequential Logic ◽

Path Delay Test

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Efficient path delay test generation based on stuck-at test generation using checker circuitry

2007 IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.2007.4397301 ◽

2007 ◽

Author(s):

Tsuyoshi Iwagaki ◽

Satoshi Ohtake ◽

Mineo Kaneko ◽

Hideo Fujiwara

Keyword(s):

Test Generation ◽

Path Delay Test

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Mixed structural-functional path delay test generation and compaction

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ◽

10.1109/dft.2013.6653575 ◽

2013 ◽

Author(s):

Kun Bian ◽

D. M. H. Walker ◽

Sunil P. Khatri ◽

Shayak Lahiri

Keyword(s):

Test Generation ◽

Path Delay Test

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Logic systems for path delay test generation

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference ◽

10.1109/eurdac.1993.410638 ◽

2002 ◽

Author(s):

S. Bose ◽

P. Agrawal ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Logic Systems ◽

Path Delay Test

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