Impact of Channel Implant Variation on RTN and Flicker Noise

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

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Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering

2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vlsi-tsa51926.2021.9440091 ◽

2021 ◽

Author(s):

Sourav De ◽

Wei-Xuan Bu ◽

Bo-Han Qiu ◽

Chung-Jun Su ◽

Yao-Jen Lee ◽

...

Keyword(s):

Flicker Noise ◽

Charge Trapping ◽

Thermal Engineering ◽

Ferroelectric Capacitors

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Analysis of Noise and Velocity in GNSS EPN-Repro 2 Time Series

Remote Sensing ◽

10.3390/rs13142783 ◽

2021 ◽

Vol 13 (14) ◽

pp. 2783

Author(s):

Sorin Nistor ◽

Norbert-Szabolcs Suba ◽

Kamil Maciuk ◽

Jacek Kudrys ◽

Eduard Ilie Nastase ◽

...

Keyword(s):

Time Series ◽

Visual Inspection ◽

Flicker Noise ◽

Vertical Component ◽

Likelihood Estimation ◽

Noise Model ◽

Noise Amplitude ◽

Allan Deviation ◽

Power Spectral ◽

Position Time Series

This study evaluates the EUREF Permanent Network (EPN) station position time series of approximately 200 GNSS stations subject to the Repro 2 reprocessing campaign in order to characterize the dominant types of noise and amplitude and their impact on estimated velocity values and associated uncertainties. The visual inspection on how different noise model represents the analysed data was done using the power spectral density of the residuals and the estimated noise model and it is coherent with the calculated Allan deviation (ADEV)-white and flicker noise. The velocities resulted from the dominant noise model are compared to the velocity obtained by using the Median Interannual Difference Adjusted for Skewness (MIDAS). The results show that only 3 stations present a dominant random walk noise model compared to flicker and powerlaw noise model for the horizontal and vertical components. We concluded that the velocities for the horizontal and vertical component show similar values in the case of MIDAS and maximum likelihood estimation (MLE), but we also found that the associated uncertainties from MIDAS are higher compared to the uncertainties from MLE. Additionally, we concluded that there is a spatial correlation in noise amplitude, and also regarding the differences in velocity uncertainties for the Up component.

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Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽

10.3390/electronics10101156 ◽

2021 ◽

Vol 10 (10) ◽

pp. 1156

Author(s):

Lorenzo Benvenuti ◽

Alessandro Catania ◽

Giuseppe Manfredini ◽

Andrea Ria ◽

Massimo Piotto ◽

...

Keyword(s):

Low Voltage ◽

Flicker Noise ◽

Supply Voltage ◽

Cmos Process ◽

Clock Frequency ◽

Design Environment ◽

Ultra Low Power ◽

Analog Cmos ◽

Gain Error ◽

Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

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