HLS-Compatible, Embedded-Processor Stream Links

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.

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Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency

Proceedings of the 45th annual conference on Design automation - DAC '08 ◽

10.1145/1391469.1391488 ◽

2008 ◽

Cited By ~ 8

Author(s):

Houman Homayoun ◽

Sudeep Pasricha ◽

Mohammad Makhzan ◽

Alex Veidenbaum

Keyword(s):

Register File ◽

Frequency Scaling ◽

Embedded Processor ◽

Processor Performance

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Research on Fuzzy Control of Mine Ventilation Based on Embedded Systems

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.686.126 ◽

2014 ◽

Vol 686 ◽

pp. 126-131

Author(s):

Xiao Yan Sha

Keyword(s):

Fuzzy Control ◽

Control Algorithm ◽

Fuzzy Controller ◽

Simulation Analysis ◽

Control Unit ◽

Real Time Control ◽

Embedded Processor ◽

Feed Forward ◽

Time Control ◽

Software And Hardware

Taking embedded processor as the core control unit, the paper designs the fan monitoring system software and hardware to achieve the fan working condition detection and real-time control. For the control algorithm, the paper analyzes the fuzzy control system theory and composition, and then combined with tunnel ventilation particularity, introduce feed-forward model to predict the incremental acquisition of pollutants to reduce lag, combined with the system feedback value and the set value, by calculate of two independent computing fuzzy controller, and ultimately determine the number of units increase or decrease in the tunnel jet fans start and stop. Through simulation analysis, the introduction of a feed-forward signal, it can more effectively improve the capability of the system impact of interference.

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Efficient RGB to YCbCr Color Space Conversion for Embedded Application

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.543-547.2873 ◽

2014 ◽

Vol 543-547 ◽

pp. 2873-2878

Author(s):

Hui Yong Li ◽

Hong Xu Jiang ◽

Ping Zhang ◽

Han Qing Li ◽

Qian Cao

Keyword(s):

Direct Method ◽

Color Space ◽

Video Data ◽

Floating Point ◽

Portable Devices ◽

Embedded Processor ◽

Color Space Conversion ◽

Ycbcr Color Space ◽

Original Approach ◽

General Method

Modern embedded portable devices usually have to deal with large amounts of video data. Due to massive floating-point multiplications, the color space conversion is inefficient on the embedded processor. Considering the characteristics of RGB to YCbCr color space conversion, this paper proposed a strategy for truncated-based LUT Multiplier (T-LUT Multiplier). On this base, an original approach converting RGB to YCbCr is presented which employs the T-LUT Multiplier and the pipeline-based adder. Experimental results demonstrate that the proposed method can obtain maximum operating frequency of 358MHz, 3.5 times faster than the direct method. Furthermore, the power consumption is less than that of the general method approximately by 15%~27%.

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Design of Online Pipeline Ultrasonic Data Acquisition and Storage System Based on PCI Bus

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.651-653.2296 ◽

2014 ◽

Vol 651-653 ◽

pp. 2296-2300

Author(s):

Jing Huang ◽

She Yu Zhou ◽

Bing Lei Guan

Keyword(s):

Data Acquisition ◽

Ultrasonic Testing ◽

High Speed ◽

Storage System ◽

Ultrasonic Signal ◽

Pci Bus ◽

Online Data ◽

Embedded Processor ◽

Design Scheme ◽

And Storage

Based on the theory of ultrasonic testing, an online data-acquisition and storage system is designed. The design scheme of hardware and software of the system is introduced in this paper, in which the embedded processor DSP and FPGA is used as its control core and the interface of PCI bus and DSP is designed. Thus a high speed and large-capacity ultrasonic signal can be processed, furthermore the pipelines defects can be analyze and evaluate.

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