Row/column pattern sensitive fault detection in RAMs via built-in self-test

2003 ◽  
Author(s):  
M. Franklin ◽  
K.K. Saluja ◽  
K. Kinoshita
Keyword(s):  
Fault Detection ◽  
Self Test ◽  
Built In Self Test

Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection

2019 ◽  
Author(s):  
Mehmet Ince ◽  
Ender Yilmaz ◽  
Wei Fu ◽  
Joonsung Park ◽  
Krishnaswamy Nagaraj ◽  
...  
Keyword(s):  
Fault Detection ◽  
Self Test ◽  
Built In Self Test

scholarly journals Syndrome Signature in Output Compaction for VLSI Built-in Self-Test

VLSI Design ◽  
1998 ◽  
Vol 7 (2) ◽  
pp. 191-201
Author(s):  
Sunil R. Das ◽  
Nita Goel ◽  
Wen B. Jone ◽  
Amiya R. Nayak
Keyword(s):  
Fault Detection ◽  
Vlsi Circuits ◽  
Internal Line ◽  
Single Output ◽  
Signature Generation ◽  
Self Testing ◽  
Vlsi Technology ◽  
Self Test ◽  
Built In Self Test

In this paper, we focus on the use of signature-based output compaction technique for built-in self-testing of VLSI circuits. We give algorithm for single-output and multiple-output signature generation using exhaustive test patterns extending the syndrome conccpt. The signature wc develop is a functional signature and is very effective for both input and internal line fault detection, as seen from simulation on various benchmark circuits. The signature generators can bc easily implemented using the current VLSI technology.

Built-in Self-Test Design for Fault Detection of MUXFXs in SRAM-Based FPGAs

2010 ◽  
Vol 39 ◽  
pp. 220-225
Author(s):  
Sheng Hong ◽  
Wen Hui Tao ◽  
Yun Ping Qi ◽  
Cheng Gao ◽  
Xiao Zhang Liu ◽  
...  
Keyword(s):  
Fault Detection ◽  
Test Pattern ◽  
Pattern Generator ◽  
Test Design ◽  
Output Response ◽  
Area Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
Logic Blocks

This paper proposes a built-in self-test (BIST) design for MUXFXs in SRAM-based FPGAs. This approach can test both the interconnect resources and MUXFXs in the configurable logic blocks (CLBs). Because the test pattern generator (TPG) and output response analyzer (ORA)are configured by existing CLBs in FPGAs, no extra area overhead is needed for the proposed BIST structure. Open/short , stuck on/off faults in PSs, and stuck-at-0/1 faults in MUXFXs will be detected through the target fault detection/diagnosis of the proposed BIST structure.

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