scholarly journals Syndrome Signature in Output Compaction for VLSI Built-in Self-Test

VLSI Design ◽  
1998 ◽  
Vol 7 (2) ◽  
pp. 191-201
Author(s):  
Sunil R. Das ◽  
Nita Goel ◽  
Wen B. Jone ◽  
Amiya R. Nayak
Keyword(s):  
Fault Detection ◽  
Vlsi Circuits ◽  
Internal Line ◽  
Single Output ◽  
Signature Generation ◽  
Self Testing ◽  
Vlsi Technology ◽  
Self Test ◽  
Built In Self Test

In this paper, we focus on the use of signature-based output compaction technique for built-in self-testing of VLSI circuits. We give algorithm for single-output and multiple-output signature generation using exhaustive test patterns extending the syndrome conccpt. The signature wc develop is a functional signature and is very effective for both input and internal line fault detection, as seen from simulation on various benchmark circuits. The signature generators can bc easily implemented using the current VLSI technology.

Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection

2019 ◽  
Author(s):  
Mehmet Ince ◽  
Ender Yilmaz ◽  
Wei Fu ◽  
Joonsung Park ◽  
Krishnaswamy Nagaraj ◽  
...  
Keyword(s):  
Fault Detection ◽  
Self Test ◽  
Built In Self Test

Built-in Self-Test Design for Fault Detection of MUXFXs in SRAM-Based FPGAs

2010 ◽  
Vol 39 ◽  
pp. 220-225
Author(s):  
Sheng Hong ◽  
Wen Hui Tao ◽  
Yun Ping Qi ◽  
Cheng Gao ◽  
Xiao Zhang Liu ◽  
...  
Keyword(s):  
Fault Detection ◽  
Test Pattern ◽  
Pattern Generator ◽  
Test Design ◽  
Output Response ◽  
Area Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
Logic Blocks

This paper proposes a built-in self-test (BIST) design for MUXFXs in SRAM-based FPGAs. This approach can test both the interconnect resources and MUXFXs in the configurable logic blocks (CLBs). Because the test pattern generator (TPG) and output response analyzer (ORA)are configured by existing CLBs in FPGAs, no extra area overhead is needed for the proposed BIST structure. Open/short , stuck on/off faults in PSs, and stuck-at-0/1 faults in MUXFXs will be detected through the target fault detection/diagnosis of the proposed BIST structure.

A Concurrent Built-In Self-Test Architecture Based on a Self-Testing RAM

2005 ◽  
Vol 54 (1) ◽  
pp. 69-78 ◽  
Author(s):  
I. Voyiatzis ◽  
A. Paschalis ◽  
D. Gizopoulos ◽  
N. Kranitis ◽  
C. Halatsis
Keyword(s):  
Self Testing ◽  
Self Test ◽  
Built In Self Test ◽  
Test Architecture

Picosecond Imaging Circuit Analysis of the IBM G6 Microprocessor Cache

1999 ◽  
Author(s):  
Moyra McManus ◽  
Pia Sanda ◽  
Steven Steen ◽  
Dan Knebel ◽  
Dennis Manzer ◽  
...  
Keyword(s):  
Circuit Analysis ◽  
Vlsi Circuits ◽  
New Technique ◽  
High Frequencies ◽  
Early Design ◽  
Race Condition ◽  
Self Test ◽  
Built In Self Test ◽  
Control Circuits ◽  
A New Technique

Abstract Picosecond Imaging Circuit Analysis (PICA) is a new technique shown here to be applicable to the analysis of complex VLSI circuits. PICA was used to diagnose a timing failure in the early design of the G6 microprocessor chip. The fault occurred at high frequencies upon consecutive writes. Using PICA, combined with programmable array built-in self test (RAMBIST) techniques, the problem was traced to a race condition in the write control circuits. This allowed timely correction of the design for product implementation.

scholarly journals A ΣΔ Closed-Loop Interface for a MEMS Accelerometer with Digital Built-In Self-Test Function

Micromachines ◽  
2018 ◽  
Vol 9 (9) ◽  
pp. 444 ◽  
Author(s):  
Dongliang Chen ◽  
Xiaowei Liu ◽  
Liang Yin ◽  
Yinhang Wang ◽  
Zhaohe Shi ◽  
...  
Keyword(s):  
Closed Loop ◽  
Process Condition ◽  
Laboratory Equipment ◽  
Interface Circuit ◽  
Mems Accelerometer ◽  
Self Testing ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip

Sigma-delta (ΣΔ) closed-loop operation is the best candidate for realizing the interface circuit of MEMS accelerometers. However, stability and reliability problems are still the main obstacles hindering its further development for high-end applications. In situ self-testing and calibration is an alternative way to solve these problems in the current process condition, and thus, has received a lot of attention in recent years. However, circuit methods for self-testing of ΣΔ closed-loop accelerometers are rarely reported. In this paper, we propose a fifth-order ΣΔ closed-loop interface for a capacitive MEMS accelerometer. The nonlinearity problem of the system is detailed discussed, the source of it is analyzed, and the solutions are given. Furthermore, a built-in self-test (BIST) unit is integrated on-chip for in situ self-testing of the loop distortion. In BIST mode, a digital electrostatic excitation is generated by an on-chip digital resonator, which is also ΣΔ modulated. By single-bit ΣΔ-modulation, the noise and linearity of excitation is effectively improved, and a higher detection level for distortion is easily achieved, as opposed to the physical excitation generated by the motion of laboratory equipment.

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