An innovation tool-chain for synthesis and implementation of Xilinx FPGA devices

This paper describes the design and implementation of an ARM based embedded operating system micro kernel developed on Linux platform with GNU tool chain in technical details, including the three-layer architecture of the kernel (boot layer, core layer and task layer), multi-task schedule (priority for real-time and round-robin for time-sharing), IRQ handler, SWI handler, system calls, and inter-task communication based on which the micro-kernel architecture is constructed. On the foundation of this micro kernel, more components essential to a practical operating system, such as file system and TCP/IP processing, can be added in order to form a real and practical multi-task micro-kernel embedded operating system.

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MicroBlaze-Based Multiprocessor Embedded Cryptosystem on FPGA for Elliptic Curve Scalar Multiplication Over Fp

Journal of Circuits System and Computers ◽

10.1142/s0218126619500373 ◽

2019 ◽

Vol 28 (03) ◽

pp. 1950037 ◽

Cited By ~ 3

Author(s):

A. Bellemou ◽

N. Benblidia ◽

M. Anane ◽

M. Issad

Keyword(s):

Elliptic Curve ◽

Scalar Multiplication ◽

Security Level ◽

Prime Field ◽

Montgomery Modular Multiplication ◽

Parallel Implementations ◽

High Radix ◽

System On Programmable Chip ◽

Xilinx Fpga ◽

Elliptic Curve Scalar Multiplication

In this paper, we present Microblaze-based parallel architectures of Elliptic Curve Scalar Multiplication (ECSM) computation for embedded Elliptic Curve Cryptosystem (ECC) on Xilinx FPGA. The proposed implementations support arbitrary Elliptic Curve (EC) forms defined over large prime field ([Formula: see text]) with different security-level sizes. ECSM is performed using Montgomery Power Ladder (MPL) algorithm in Chudnovsky projective coordinates system. At the low abstraction level, Montgomery Modular Multiplication (MMM) is considered as the critical operation. It is implemented within a hardware Accelerator MMM (AccMMM) core based on the modified high radix, [Formula: see text] MMM algorithm. The efficiency of our parallel implementations is achieved by the combination of the mixed SW/HW approach with Multi Processor System on Programmable Chip (MPSoPC) design. The integration of multi MicroBlaze processor in single architecture allows not only the flexibility of the overall system but also the exploitation of the parallelism in ECSM computation with several degrees. The Virtex-5 parallel implementations of 256-bit and 521-bis ECSM computations run at 100[Formula: see text]MHZ frequency and consume between 2,739 and 6,533 slices, 22 and 72 RAMs and between 16 and 48 DSP48E cores. For the considered security-level sizes, the delays to perform single ECSM are between 115[Formula: see text]ms and 14.72[Formula: see text]ms.

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I-DMAC: An Intelligent DMA Controller for Utilization - Aware Video Streaming used in AI Applications

10.54216/jcim.080203 ◽

2021 ◽

pp. 60-70

Author(s):

Piyush Kumar Shukla ◽

◽

Prashant Kumar Shukla ◽

Keyword(s):

Video Processing ◽

High Performance ◽

Data Transfer ◽

Direct Memory Access ◽

Large Data ◽

Video Frame ◽

Microprocessor System ◽

Bulk Data ◽

Xilinx Fpga ◽

Vhdl Code

The interpretation of large data streams necessitates high-performance repeated transfers, which overload Microprocessor System on Chips (SoC). The effective direct memory access (DMA) controller performs bulk data transfers without the CPU's involvement. The Direct Memory Controller (DMAC) solves this by facilitating bulk data transfer and execution. In this work, we created an intelligent DMAC (I-DMAC) for accessing video processing data without using CPUs. The model includes Bus selection Module, User control signal, Status Register, DMA supported Address, and AXI-PCI subsystems for improved video frame analysis. These modules are experimentally verified in Xilinx FPGA SoC architecture using VHDL code simulation and results compared to the E-DMAC model.

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Implementation of the visual data processing algorithms for onboard computing units

Robotics and Technical Cybernetics ◽

10.31776/rtcj.9204 ◽

2021 ◽

Vol 9 (2) ◽

pp. 106-111

Author(s):

Sergey Sokolov ◽

Andrey Boguslavsky ◽

Sergei Romanenko

Keyword(s):

Vision System ◽

Fpga Implementation ◽

Visual Data ◽

Dense Optical Flow ◽

Data Capturing ◽

Computation Algorithm ◽

Modern Experience ◽

Computing Module ◽

Xilinx Fpga

According to the short analysis of modern experience of hardware and software for autonomous mobile robots a role of computer vision systems in the structure of those robots is considered. A number of configurations of onboard computers and implementation of algorithms for visual data capturing and processing are described. In original configuration space the «algorithms-hardware» plane is considered. For software designing the realtime vision system framework is used. Experiments with the computing module based on the Intel/Altera Cyclone IV FPGA (implementation of the histogram computation algorithm and the Canny's algorithm), with the computing module based on the Xilinx FPGA (implementation of a sparse and dense optical flow algorithms) are described. Also implementation of algorithm of graph segmentation of grayscale images is considered and analyzed. Results of the first experiments are presented.

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