Design of low-jitter clock duty cycle stabilizer in high-performance pipelined ADC

Author(s):  
Mingwen Zhang ◽  
Yongsheng Yin ◽  
Honghui Deng ◽  
Hongmei Chen
2018 ◽  
Vol 19 ◽  
pp. 170-184 ◽  
Author(s):  
Quirin Kellner ◽  
Daniel Worwood ◽  
Anup Barai ◽  
Widanalage Dhammika Widanage ◽  
James Marco

Author(s):  
D. J. K. Stuart

The highway vehicle is concerned with transporting persons or freight over substantial distances, usually at as high an average speed as the conditions will permit. The high-performance private car and the door-to-door delivery vehicle represent opposite ends of the scale of the duty cycle. In the latter case, the very cycle itself—stop-start characteristics, the high percentage of standing time resulting in relatively small mileage, and the small penalty of limited maximum speed—represents cumulative factors in respect of which the basic economics of the battery-operated electric vehicle dominates other considerations. Thus, in order to arrive at design specifications it is essential to consider the duty cycle which, in the case of all types of industrial vehicle, is characterized by the need to execute a high proportion of forward/reverse manoeuvres, long periods of low-speed operation, and the provision of an increasing complexity of powered auxiliary equipment.


2013 ◽  
Vol 60 (9) ◽  
pp. 557-561 ◽  
Author(s):  
Chang-kyo Lee ◽  
Wan Kim ◽  
Hyunwook Kang ◽  
Seung-Tak Ryu

Micromachines ◽  
2022 ◽  
Vol 13 (1) ◽  
pp. 114
Author(s):  
Dongdong Chen ◽  
Xinhui Cui ◽  
Qidong Zhang ◽  
Di Li ◽  
Wenyang Cheng ◽  
...  

As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.


2004 ◽  
Vol 13 (03) ◽  
pp. 443-466
Author(s):  
JABER A. ABU-QAHOUQ ◽  
HONG MAO ◽  
ISSA BATARSEH

Point-of-load DC–DC converter requirements and design are increasingly becoming stricter than ever. This is due to the required tight dynamic tolerances allowed for supply voltages and high dynamic performance demand coupled with very high power density. Moreover, as the required converter output voltage becomes smaller, higher voltage step-down ratio is required, which results in smaller switching duty cycle in the nonisolated topologies. Step-down transformer with large turns ratio is used in the isolated topologies to step-down the voltage and keep larger duty cycle. Most of the nonisolated DC–DC topologies are buck-derived and unfortunately work at hard-switching which degrades the efficiency. DC–DC interleaved buck topologies were proposed but are highly sensitive to interleaved phases asymmetry and require high performance current sharing loop. In this paper, a nonisolated multiphase nonisolated half-bridge-buck topology is presented. This topology makes it possible to achieve soft-switching, works at larger switching duty cycle with lower output voltages, and does not require current sharing loop because of the inherent current sharing capability. Moreover, a coupled-inductor current doubler topology is also presented in this paper allowing higher step-down ratio and lower output current ripple. Theoretical analysis and experimental results are presented.


2014 ◽  
Vol 11 (2) ◽  
pp. 20148002-20148002
Author(s):  
Jingyu Wang ◽  
Zhangming Zhu ◽  
Guangwen Yu ◽  
Huaxi Gu ◽  
Lianxi Liu ◽  
...  

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