Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors

2015 ◽  
Author(s):  
Mahanama Wickramasinghe ◽  
Hui Guo
Keyword(s):  
Power Efficiency ◽  
High Performance ◽  
Embedded Processors ◽  
Application Specific ◽  
Thread Synchronization

NTB branch predictor: dynamic branch predictor for high-performance embedded processors

2014 ◽  
Vol 72 (5) ◽  
pp. 1679-1693 ◽  
Author(s):  
Cong Thuan Do ◽  
Hong Jun Choi ◽  
Dong Oh Son ◽  
Jong Myon Kim ◽  
Cheol Hong Kim
Keyword(s):  
High Performance ◽  
Embedded Processors ◽  
Branch Predictor

Design Tools for Application Specific Embedded Processors

2002 ◽  
pp. 319-333 ◽  
Author(s):  
Wei Qin ◽  
Subramanian Rajagopalan ◽  
Manish Vachharajani ◽  
Hangsheng Wang ◽  
Xinping Zhu ◽  
...  
Keyword(s):  
Embedded Processors ◽  
Design Tools ◽  
Application Specific

scholarly journals High Performance Multistring Converter Topology for Three-Phase Grid Tied 200 kW Photovoltaic Generating System

2017 ◽  
Vol 1 (2) ◽  
Author(s):  
Mohammad Rustam M. L. ◽  
F. Danang Wijaya
Keyword(s):  
Power Efficiency ◽  
High Performance ◽  
Reactive Power ◽  
Simulation Method ◽  
Operating Conditions ◽  
Total System ◽  
Voltage Reference ◽  
Pv System ◽  
Three Phase ◽  
Converter Topology

Under various external conditions, grid connected PV system performance is strongly affected by the topology that is used to connect a PV system with grid. This research aims to design a multistring based converter topology for three-phase grid connected 200 kW PV system that has a high performance in various operating conditions. Research was done by a simulation method using Matlab-Simulink with performance being evaluated including the generated power, efficiency, power quality in accordance with grid requirements, as well as the power flow. In the simulation, multistring converter topology was designed using two dc-dc boost multistring converters connected in parallel to a centralized of three-phase three-level NPC inverter with the size of the string being shorter and more parallel strings as well as the maximum voltage of the PV array of 273.5 V close to dc voltage reference of 500 V. Each dc-dc boost multistring converter have individual MPPT controllers. The simulation results showed that this multistring converter topology had a high performance in various operating conditions. This due to more power generated by the NPC inverter (> 190 kW) at the time of high power generation on the STC conditions (1000 W/m2, 25 oC), the lowest efficiency of the total system is 95.08 % and the highest efficiency of the total system is 99.4 %, the quality of the power generated in accordance with the requirements of grid, as well as the inverter put more active power to the grid and less reactive power to the grid. The response of the inverter slightly worse for loads with greater reactive power and unbalanced.

Rack Server Solution in Data Center

2015 ◽  
Author(s):  
Sheng Kang ◽  
Guofeng Chen ◽  
Chun Wang ◽  
Ruiquan Ding ◽  
Jiajun Zhang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Data Center ◽  
Power Efficiency ◽  
High Performance ◽  
High Efficiency ◽  
High Growth ◽  
General Purpose ◽  
Power Supplies

With the advent of big data and cloud computing solutions, enterprise demand for servers is increasing. There is especially high growth for Intel based x86 server platforms. Today’s datacenters are in constant pursuit of high performance/high availability computing solutions coupled with low power consumption and low heat generation and the ability to manage all of this through advanced telemetry data gathering. This paper showcases one such solution of an updated rack and server architecture that promises such improvements. The ability to manage server and data center power consumption and cooling more completely is critical in effectively managing datacenter costs and reducing the PUE in the data center. Traditional Intel based 1U and 2U form factor servers have existed in the data center for decades. These general purpose x86 server designs by the major OEM’s are, for all practical purposes, very similar in their power consumption and thermal output. Power supplies and thermal designs for server in the past have not been optimized for high efficiency. In addition, IT managers need to know more information about servers in order to optimize data center cooling and power use, an improved server/rack design needs to be built to take advantage of more efficient power supplies or PDU’s and more efficient means of cooling server compute resources than from traditional internal server fans. This is the constant pursuit of corporations looking at new ways to improving efficiency and gaining a competitive advantage. A new way to optimize power consumption and improve cooling is a complete redesign of the traditional server rack. Extracting internal server power supplies and server fans and centralizing these within the rack aims to achieve this goal. This type of design achieves an entirely new low power target by utilizing centralized, high efficiency PDU’s that power all servers within the rack. Cooling is improved by also utilizing large efficient rack based fans for airflow to all servers. Also, opening up the server design is to allow greater airflow across server components for improved cooling. This centralized power supply breaks through the traditional server power limits. Rack based PDU’s can adjust the power efficiency to a more optimum point. Combine this with the use of online + offline modes within one single power supply. Cold backup makes data center power to achieve optimal power efficiency. In addition, unifying the mechanical structure and thermal definitions within the rack solution for server cooling and PSU information allows IT to collect all server power and thermal information centrally for improved ease in analyzing and processing.

High-Performance Reconfigurable Computing

2019 ◽  
pp. 731-744
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-performance reconfigurable computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to general-purpose processors. Better performance and lower power consumption could be achieved using application-specific integrated circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter, the authors provide a description of reconfigurable hardware for high-performance computing.

High-Performance Reconfigurable Computing

2018 ◽  
pp. 4018-4029
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-Performance Reconfigurable Computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to General-Purpose Processors. Better performance and lower power consumption could be achieved using Application Specific Integrated Circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter we will provide a description of reconfigurable hardware for high performance computing.

A High-Performance and Low-Power On-Chip Network with Reconfigurable Topology

2010 ◽  
pp. 309-329
Author(s):  
Mehdi Modarressi ◽  
Hamid Sarbazi-Azad
Keyword(s):  
High Performance ◽  
Chip Multiprocessors ◽  
Optimization Methods ◽  
Critical Feature ◽  
Design Constraints ◽  
Core System ◽  
Traffic Pattern ◽  
On Chip ◽  
Network Mapping ◽  
Application Specific

In this chapter, we present a reconfigurable architecture for network-on-chips (NoC) on which arbitrary application-specific topologies can be implemented. The proposed NoC can dynamically tailor its topology to the traffic pattern of different applications, aiming to address one of the main drawbacks of existing application-specific NoC optimization methods, i.e. optimizing NoCs based on the traffic pattern of a single application. Supporting multiple applications is a critical feature of an NoC as several different applications are integrated into the modern and complex multi-core system-on-chips and chip multiprocessors and an NoC that is designed to run exactly one application does not necessarily meet the design constraints of other applications. The proposed NoC supports multiple applications by configuring as a topology which matches the traffic pattern of the currently running application in the best way. In this chapter, we first introduce the proposed reconfigurable topology and then address the two problems of core to network mapping and topology exploration. Experimental results show that this architecture effectively improves the performance of NoCs and reduces power consumption.

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