Low power look-up table topologies for FPGAs

2014 ◽  
Author(s):  
Thadigotla Venkata Subbareddy ◽  
Bommepalli Madhava Reddy ◽  
Har Narayan Upadhyay ◽  
V Elamaran
Keyword(s):  
Low Power ◽  
Look Up Table

Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

2016 ◽  
Vol 10 (3) ◽  
pp. 163-172 ◽  
Author(s):  
Zarrin Tasnim Sworna ◽  
Mubin UlHaque ◽  
Nazma Tara ◽  
Hafiz Md. Hasan Babu ◽  
Ashis Kumar Biswas
Keyword(s):  
Low Power ◽  
Field Programmable Gate Array ◽  
Look Up Table ◽  
Field Programmable ◽  
Decimal Adder ◽  
Gate Array ◽  
Area Efficient

Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design

Integration ◽  
2018 ◽  
Vol 62 ◽  
pp. 1-13 ◽  
Author(s):  
P. Singh ◽  
B.S. Reniwal ◽  
V. Vijayvargiya ◽  
V. Sharma ◽  
S.K. Vishvakarma
Keyword(s):  
Low Power ◽  
Positive Feedback ◽  
High Stability ◽  
Ultra Low Power ◽  
Look Up Table ◽  
Sram Cell
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