Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications

2015 ◽  
Author(s):  
Hammam Orabi ◽  
Nasir Shaikh-Husin ◽  
U. U. Sheikh
Keyword(s):  
Real Time ◽  
Low Cost ◽  
Fpga Architecture ◽  
Harris Corner ◽  
Harris Corner Detector ◽  
Real Time Applications

Study on a Real-Time Corner Detection Algorithm

2010 ◽  
Vol 159 ◽  
pp. 192-197
Author(s):  
Yong Fang Guo ◽  
Ming Yu ◽  
Yi Cai Sun
Keyword(s):  
Real Time ◽  
Computation Time ◽  
Detection Algorithm ◽  
Corner Detection ◽  
Test Results ◽  
Multigrid Algorithm ◽  
Autocorrelation Matrix ◽  
Harris Corner ◽  
Harris Corner Detector ◽  
Real Time Applications

Conventional Harris corner detector is a desirable detector but it requires significantly more computation time. For MIC detector proposed by Trajkovic, the minimal computational demands of its operator make it well-suited for real-time applications, however the Trajkovic’s operator responses too readily to certain diagonal edges. For this reason, the paper proposed a new corner detection algorithm. The new corner detection algorithm adopted multigrid algorithm and preprocessed the lower resolution revision of the original image to obtain the potential corners, subsequently used autocorrelation matrix to get the corner response function for the corresponding points of the potential corner. The test results indicate the new corner detection algorithm can decrease edge responses and the number of textural corners effectively. Furthermore, it can satisfy the demands of real-time applications.

scholarly journals Real-time Neural Networks Implementation Proposal for Microcontrollers

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1597
Author(s):  
Caio José B. V. Guimarães ◽  
Marcelo A. C. Fernandes
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Intelligent Systems ◽  
Implementation Strategy ◽  
Processing Time ◽  
Mean Squared Error ◽  
Low Cost ◽  
Real Time Applications ◽  
Time Required ◽  
Process Classification

The adoption of intelligent systems with Artificial Neural Networks (ANNs) embedded in hardware for real-time applications currently faces a growing demand in fields such as the Internet of Things (IoT) and Machine to Machine (M2M). However, the application of ANNs in this type of system poses a significant challenge due to the high computational power required to process its basic operations. This paper aims to show an implementation strategy of a Multilayer Perceptron (MLP)-type neural network, in a microcontroller (a low-cost, low-power platform). A modular matrix-based MLP with the full classification process was implemented as was the backpropagation training in the microcontroller. The testing and validation were performed through Hardware-In-the-Loop (HIL) of the Mean Squared Error (MSE) of the training process, classification results, and the processing time of each implementation module. The results revealed a linear relationship between the values of the hyperparameters and the processing time required for classification, also the processing time concurs with the required time for many applications in the fields mentioned above. These findings show that this implementation strategy and this platform can be applied successfully in real-time applications that require the capabilities of ANNs.

scholarly journals LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 81 ◽  
Author(s):  
Alberto Sanchez ◽  
Angel de Castro ◽  
Maria Sofía Martínez-García ◽  
Javier Garrido
Keyword(s):  
Real Time ◽  
Low Cost ◽  
Power Converter ◽  
Buck Converter ◽  
Digital Design ◽  
Floating Point ◽  
Hardware In The Loop ◽  
Time Simulation ◽  
Real Time Applications ◽  
Plant Power

One of the main decisions when making a digital design is which arithmetic is going to be used. The arithmetic determines the hardware resources needed and the latency of every operation. This is especially important in real-time applications like HIL (Hardware-in-the-loop), where a real-time simulation of a plant—power converter, mechanical system, or any other complex system—is accomplished. While a fixed-point gets optimal implementations, using considerably fewer resources and allowing smaller simulation steps, its use is very restricted to very specific applications, as its design effort is quite high. On the other side, IEEE-754 floating-point may have resolution problems in case of the 32-bit version, and excessive hardware usage in case of the 64-bit version. This paper presents LOCOFloat, a low-cost floating-point format designed for FPGA applications. Its key features are soft normalization of the results, using significand and exponent fields in two’s complement. This paper shows the implementation of addition, subtraction and multiplication of the proposed format. Both IEEE-754 versions and LOCOFloat are compared in this paper, implementing a HIL model of a buck converter. Although the application example is a HIL simulator, other applications could take benefit from the proposed format. Results show that LOCOFloat is as accurate as 64-bit floating-point, while reducing the use of DSPs blocks by 84 % .

scholarly journals Evaluation of accurate eye corner detection methods for gaze estimation

2014 ◽  
Vol 7 (3) ◽  
Author(s):  
Jose Javier Bengoechea ◽  
Juan J. Cerrolaza ◽  
Arantxa Villanueva ◽  
Rafael Cabeza
Keyword(s):  
Neural Network ◽  
High Performance ◽  
Low Cost ◽  
Corner Detection ◽  
Detection Methods ◽  
Gaze Estimation ◽  
Harris Corner ◽  
Feature Based ◽  
Harris Corner Detector ◽  
Iris Center

Accurate detection of iris center and eye corners appears to be a promising approach for low cost gaze estimation. In this paper we propose novel eye inner corner detection methods. Appearance and feature based segmentation approaches are suggested. All these methods are exhaustively tested on a realistic dataset containing images of subjects gazing at different points on a screen. We have demonstrated that a method based on a neural network presents the best performance even in light changing scenarios. In addition to this method, algorithms based on AAM and Harris corner detector present better accuracies than recent high performance face points tracking methods such as Intraface.

scholarly journals An experimental study of fog and cloud computing in CEP-based Real-Time IoT applications

2021 ◽  
Vol 10 (1) ◽  
Author(s):  
Giovanny Mondragón-Ruiz ◽  
Alonso Tenorio-Trigoso ◽  
Manuel Castillo-Cara ◽  
Blanca Caminero ◽  
Carmen Carrión
Keyword(s):  
Real Time ◽  
Event Detection ◽  
Low Cost ◽  
Fog Computing ◽  
Iot Applications ◽  
Local Resources ◽  
Latency Analysis ◽  
Real Time Applications ◽  
Time Required ◽  
Processing Architecture

AbstractInternet of Things (IoT) has posed new requirements to the underlying processing architecture, specially for real-time applications, such as event-detection services. Complex Event Processing (CEP) engines provide a powerful tool to implement these services. Fog computing has raised as a solution to support IoT real-time applications, in contrast to the Cloud-based approach. This work is aimed at analysing a CEP-based Fog architecture for real-time IoT applications that uses a publish-subscribe protocol. A testbed has been developed with low-cost and local resources to verify the suitability of CEP-engines to low-cost computing resources. To assess performance we have analysed the effectiveness and cost of the proposal in terms of latency and resource usage, respectively. Results show that the fog computing architecture reduces event-detection latencies up to 35%, while the available computing resources are being used more efficiently, when compared to a Cloud deployment. Performance evaluation also identifies the communication between the CEP-engine and the final users as the most time consuming component of latency. Moreover, the latency analysis concludes that the time required by CEP-engine is related to the compute resources, but is nonlinear dependent of the number of things connected.

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