The behavior of basic CMOS combinational gates in the presence of a floating gate defect is
characterized in order to investigate its detectability by IDDQ
. The defect is modeled at the
circuit level by the poly-bulk and metal-poly capacitances, which determine the quiescent
power supply current consumption (IDDQ
) of the defective circuit. The testing implications
on the type of defective gate are studied. Experimental measures have been made on basic
CMOS combinational modules designed with intentional floating gate defects. A good agreement
is observed between the simulation results and the experimental data. A conventional
ATPG for stuck-at faults is used to obtain the required exciting vector to test the floating gate
defects by IDDQ
Testing.
Dynamic Power Supply Current Testing for Open Defects in CMOS SRAMs