A novel wafer level hermetic packaging for MEMS devices using micro glass cavities fabricated by a hot forming process

2010 ◽  
Author(s):  
Di Zhang ◽  
Jintang Shang ◽  
Boyin Chen ◽  
Chao Xu ◽  
Junwen Liu ◽  
...  
Keyword(s):  
Hot Forming ◽  
Mems Devices ◽  
Wafer Level ◽  
Forming Process ◽  
Hermetic Packaging

On Hermeticity Detection of Wafer Level Packages for MEMS Devices

2005 ◽  
Author(s):  
A. Goswami ◽  
B. Han ◽  
C. Wade ◽  
A. Chien
Keyword(s):  
Mems Devices ◽  
Rate Measurement ◽  
Wafer Level ◽  
Measurement Sensitivity ◽  
Leak Test ◽  
Design Assessment ◽  
Hermetic Packaging ◽  
Wafer Level Packaging ◽  
Test Parameters ◽  
Leak Testing

Wafer level packaging has emerged as one of the promising solutions for hermetic packaging of MEMS devices. Detection of the level of hermeticity of the package is essential for reliability and design assessment of the devices. Traditionally, hermeticity has been tested using Helium based fine leak testing. However, there are limitations when this technique is used for the hermeticity detection of small volumes (< 10−3 cc) that are typical in wafer level packages. This paper reviews the helium fine leak test, its limitations and the influence of the different test parameters on leakage rate measurement are analyzed for wafer level packages with small cavity volumes. The results indicate a need for development of a new hermeticity measurement technique to achieve the measurement sensitivity required for wafer level packages.

Wafer Level Hermetic Packaging for RF-MEMS Devices Using Electroplated Gold Layers

2006 ◽  
pp. 617-620
Author(s):  
Gil Soo Park ◽  
Ji Hyuk Yu ◽  
Sang Won Seo ◽  
Woo Beom Choi ◽  
Kyeong Kap Paek ◽  
...  
Keyword(s):  
Rf Mems ◽  
Mems Devices ◽  
Wafer Level ◽  
Hermetic Packaging

Low Cost Fabrication of Micro Glass Cavities For MEMS Wafer Level and Hermetic Packaging

2011 ◽  
Vol 483 ◽  
pp. 23-33
Author(s):  
Jin Tang Shang ◽  
Jun Wen Liu ◽  
Di Zhang ◽  
Bo Yin Chen ◽  
Chao Xu ◽  
...  
Keyword(s):  
Process Parameters ◽  
Low Cost ◽  
Leakage Rate ◽  
Glass Wafer ◽  
Mems Devices ◽  
Wafer Level ◽  
Hermetic Packaging ◽  
Moving Parts

Many MEMS devices including accelerometer and gyroscopes, having moving parts, requires hermetic and low cost packaging. In this paper we propose a low cost fabricating process to prepare micro glass cavity arrays for wafer-level and hermetic packaging of MEMS. First, the fundamental of the process was discussed. Then, the process for preparing cavity arrays in Pyrex7740 glass wafer was studied experimentally. After that, the defects of the fabrication were discussed. Results show that wafer-level packaged cavities were prepared, whose diameter was controllably between 200 microns and 2000 microns. It is also disclosed that the defects could be avoided by controlling the process parameters. Results also show that the leakage rate of the single packaged cavities is below 5Χ10-9 Pa.m/s which could meet the hermetic packaging standard.

Hermetic Packaging Technique Featuring Through-Wafer Interconnects and Low Temperature Direct Bond

2008 ◽  
Author(s):  
James Lee ◽  
Tony Rogers
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
High Strength ◽  
Mems Devices ◽  
Wafer Level ◽  
Direct Bond ◽  
Hermetic Packaging ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Silicon Silicon

A novel wafer level packaging method suitable for low production volumes, R&D, and multi-project wafers is presented, providing a hermetic seal suitable for vacuum encapsulation with wafers bonded at a low temperature. Hermetic through-wafer interconnects are bump bonded to a CMOS chip encapsulated by bonding a cap wafer after activating surfaces with free radicals, the Silicon-Silicon direct bond is then annealed to a high strength at 200°C to avoid chip damage. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for human implantation of integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through-wafer interconnection. Solid electroplated through-wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. A key feature of this packaging method is it’s versatility, the proposed embodiment features chip to wafer bonding with an ASIC, but the package is equally suitable for MEMS devices and also for wafer to wafer bonding.

A Novel Wafer-Level Hermetic Packaging for MEMS Devices

2007 ◽  
Vol 30 (4) ◽  
pp. 616-621 ◽  
Author(s):  
Chingfu Tsou ◽  
Hungchung Li ◽  
Hsing-Cheng Chang
Keyword(s):  
Mems Devices ◽  
Wafer Level ◽  
Hermetic Packaging

Wafer Level Hermetic Packaging for RF-MEMS Devices Using Electroplated Gold Layers

2006 ◽  
Vol 326-328 ◽  
pp. 617-620
Author(s):  
Gil Soo Park ◽  
Ji Hyuk Yu ◽  
Sang Won Seo ◽  
Woo Beom Choi ◽  
Kyeong Kap Paek ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Rf Mems ◽  
Gold Films ◽  
Mems Devices ◽  
Wafer Level ◽  
Promising Technique ◽  
Hermetic Packaging ◽  
Thermocompression Bonding ◽  
Via Hole

Thermocompression bonding of electroplated gold is a promising technique for achieving low temperature, wafer level hermetic bonding without the application of an electric field or high temperature. Silicon wafers were completely bonded at 320 at a pressure of 2.5. The interconnection between the packaged devices and external terminal did not need metal filling and was made by gold films deposited on the sidewall of the via-hole. In the hermeticity test, packaged wafers had the leak rate of 2.74 ± 0.61 × 10-11 Pa m3/s. In the result of application in packaging of FBAR filter, the insertion loss is increased from -0.75dB to -1.09dB at 1.9.

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