On Hermeticity Detection of Wafer Level Packages for MEMS Devices

2005 ◽  
Author(s):  
A. Goswami ◽  
B. Han ◽  
C. Wade ◽  
A. Chien
Keyword(s):  
Mems Devices ◽  
Rate Measurement ◽  
Wafer Level ◽  
Measurement Sensitivity ◽  
Leak Test ◽  
Design Assessment ◽  
Hermetic Packaging ◽  
Wafer Level Packaging ◽  
Test Parameters ◽  
Leak Testing

Wafer level packaging has emerged as one of the promising solutions for hermetic packaging of MEMS devices. Detection of the level of hermeticity of the package is essential for reliability and design assessment of the devices. Traditionally, hermeticity has been tested using Helium based fine leak testing. However, there are limitations when this technique is used for the hermeticity detection of small volumes (< 10−3 cc) that are typical in wafer level packages. This paper reviews the helium fine leak test, its limitations and the influence of the different test parameters on leakage rate measurement are analyzed for wafer level packages with small cavity volumes. The results indicate a need for development of a new hermeticity measurement technique to achieve the measurement sensitivity required for wafer level packages.

Wafer Level Micropackaging of MEMS Devices Using Thin Film Anodic Bonding

2002 ◽  
Vol 729 ◽  
Author(s):  
Lauren E. S. Rohwer ◽  
Andrew D. Oliver ◽  
Melissa V. Collins
Keyword(s):  
Shear Strength ◽  
Test Sample ◽  
Anodic Bonding ◽  
Mems Devices ◽  
Wafer Level ◽  
Thermal Actuators ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Leak Testing ◽  
Before And After

AbstractA wafer level packaging technique that involves anodic bonding of Pyrex wafers to released surface micromachined wafers is demonstrated. Besides providing a hermetic seal, this technique allows full wafer release, provides protection during die separation, and offers the possibility of integration with optoelectronic devices. Anodic bonding was performed under applied voltages up to 1000 V, and temperatures ranging from 280 to 400°C under vacuum (10-4Torr). The quality of the bonded interfaces was evaluated using shear strength testing and leak testing. The shear strength of Pyrex-to-polysilicon and aluminum bonds was ∼10-15 MPa. The functionality of surface micromachined polysilicon devices was tested before and after anodic bonding. 100% of thermal actuators, 94% of torsional ratcheting actuators, and 70% of microengines functioned after bonding. The 70% yield was calculated from a test sample of 25 devices.

Hermetic Packaging Technique Featuring Through-Wafer Interconnects and Low Temperature Direct Bond

2008 ◽  
Author(s):  
James Lee ◽  
Tony Rogers
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
High Strength ◽  
Mems Devices ◽  
Wafer Level ◽  
Direct Bond ◽  
Hermetic Packaging ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Silicon Silicon

A novel wafer level packaging method suitable for low production volumes, R&D, and multi-project wafers is presented, providing a hermetic seal suitable for vacuum encapsulation with wafers bonded at a low temperature. Hermetic through-wafer interconnects are bump bonded to a CMOS chip encapsulated by bonding a cap wafer after activating surfaces with free radicals, the Silicon-Silicon direct bond is then annealed to a high strength at 200°C to avoid chip damage. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for human implantation of integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through-wafer interconnection. Solid electroplated through-wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. A key feature of this packaging method is it’s versatility, the proposed embodiment features chip to wafer bonding with an ASIC, but the package is equally suitable for MEMS devices and also for wafer to wafer bonding.

Wafer Level Hermetic Packaging for RF-MEMS Devices Using Electroplated Gold Layers

2006 ◽  
pp. 617-620
Author(s):  
Gil Soo Park ◽  
Ji Hyuk Yu ◽  
Sang Won Seo ◽  
Woo Beom Choi ◽  
Kyeong Kap Paek ◽  
...  
Keyword(s):  
Rf Mems ◽  
Mems Devices ◽  
Wafer Level ◽  
Hermetic Packaging

Ceramic Via Wafer-Level Packaging for MEMS

2005 ◽  
Author(s):  
John M. Heck ◽  
Leonel R. Arana ◽  
Bill Read ◽  
Thomas S. Dory
Keyword(s):  
Mems Devices ◽  
Wafer Level ◽  
Micro Electro Mechanical Systems ◽  
Mems Switches ◽  
Mems Packaging ◽  
Wafer Level Packaging ◽  
Novel Approach ◽  
Electrical Interconnection ◽  
Tin Silver Copper ◽  
Board Level

We will present a novel approach to wafer level packaging for micro-electro-mechanical systems. Like most common MEMS packaging methods today, our approach utilizes a wafer bonding process between a cap wafer and a MEMS device wafer. However, unlike the common methods that use a silicon or glass cap wafer, our approach uses a ceramic wafer with built-in metal-filled vias, that has the same size and shape as a standard 150 mm silicon wafer. This ceramic via wafer packaging method is much less complex than existing methods, since it provides hermetic encapsulation and electrical interconnection of the MEMS devices, as well as a solderable interface on the outside of the package for board-level interconnection. We have demonstrated successful ceramic via wafer-level packaging of MEMS switches using eutectic gold-tin solder as well as tin-silver-copper solder combined with gold thermo-compression bonding. In this paper, we will present the ceramic via MEMS package architecture and discuss the associated bonding and assembly processes.

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