The transformation from the development of enabling technology to mass production of
consumer-centric semiconductor products has empowered the designers to consider characteristics like
robustness, compactness, efficiency, and scalability of the product as implicit pre-cursors. The Carbon
Nanotube Field Effect Transistor (CNFET) is the present day technology. In this manuscript, we have
used CNFET as the enabling technology to design a 1-bit Full Adder (1b-FA16) with overflow detection.
The proposed 1b-FA16 is designed using 16 transistors. Finally, the proposed 1b-FA16 is further
used to design a Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) circuit and RCA with
overflow bit detection.
Methods and Results:
The proposed 1b-FA16 circuit was designed with CNFET technology simulated
at 32 nm with a voltage supply of +0.9 V using the Cadence Virtuoso CAD tool. The model used is
Stanford PTM. Comparison of the existing full adder designs with the proposed 1b-FA16 design was
done to validate the improvements in terms of power, delay and Power Delay Product (PDP). Table 2,
shows the results of comparison for the proposed 1b-FA16 with the existing full adder designs implemented
using CNFET for parameters like power, delay and power delay product.
Conclusion:
It can be concluded that the proposed 1b-FA16 yielded better results as compared to the
existing full adder designs implemented using CNFET. The improvement in power, delay and power
delay product was approximately 11%, 9% and 24% respectively. Hence, the proposed circuit implemented
using CNFET gives a substantial rate of improvements over the existing circuits.
