A Low Power Low Noise ECG Amplifier Design based on OTA

2021 ◽  
Author(s):  
Long Chen ◽  
Junying He ◽  
Feiyu Ge
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Ecg Amplifier ◽  
Amplifier Design

Low power size-efficient CMOS UWB low-noise amplifier design

2008 ◽  
Vol 51 (2) ◽  
pp. 494-496
Author(s):  
Hee-Sauk Jhon ◽  
Ickhyun Song ◽  
Jongwook Jeon ◽  
MinSuk Koo ◽  
Byung-Gook Park ◽  
...  
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Amplifier Design ◽  
Noise Amplifier

Millimeter-Wave Low-Noise Amplifier Design in 28-nm Low-Power Digital CMOS

2015 ◽  
Vol 63 (6) ◽  
pp. 1910-1922 ◽  
Author(s):  
David Fritsche ◽  
Gregor Tretter ◽  
Corrado Carta ◽  
Frank Ellinger
Keyword(s):  
Low Power ◽  
Millimeter Wave ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Digital Cmos ◽  
Amplifier Design ◽  
Noise Amplifier ◽  
28 Nm

A LOW POWER HIGH RESOLUTION ROIC DESIGN WITH 14-BIT COLUMN-LEVEL ADC FOR 384 × 288 IRFPA

2013 ◽  
Vol 22 (09) ◽  
pp. 1340015 ◽  
Author(s):  
YAJING ZHANG ◽  
WENGAO LU ◽  
GUANNAN WANG ◽  
ZHONGJIAN CHEN ◽  
YACONG ZHANG
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Low Noise ◽  
Cmos Process ◽  
Readout Integrated Circuit ◽  
Analog To Digital Conversion ◽  
Amplifier Design

A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.

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