A DC-DC boost converter with soft start function and DPEA technique using 180nm technology

In this paper, we aim to make a detailed study on the evaluation and the characteristics of the non-inverting buck–boost converter. In order to improve the behaviour of the buck-boost converter for the three operating modes, we propose an architecture based on peak current-control. Using a three modes selection circuit and a soft start circuit, this converter is able to expand the power conversion efficiency and reduce inrush current at the feedback loop. The proposed converter is designed to operate with a variable output voltage. In addition, we use LDMOS transistors with low on-resistance, which are adequate for HV applications. The obtained results show that the proposed buck-boost converter perform perfectly compared to others architecture and it is successfully implemented using 0.18 μm CMOS TSMC technology, with an output voltage regulated to 12V and input voltage range of 4-20 V. The power conversion efficiency for the three operating modes buck, boost and buck-boost are 97.6%, 96.3% and 95.5% respectively at load current of 4A.

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A Near-Threshold Voltage Startup Monolithic Boost Converter with Adaptive Sleeping Time Control

Journal of Circuits System and Computers ◽

10.1142/s0218126617500633 ◽

2016 ◽

Vol 26 (04) ◽

pp. 1750063 ◽

Cited By ~ 1

Author(s):

Lianxi Liu ◽

Yiyang Zhou ◽

Junchao Mu ◽

Xufeng Liao ◽

Zhangming Zhu ◽

...

Keyword(s):

Threshold Voltage ◽

Input Voltage ◽

Boost Converter ◽

Switching Frequency ◽

Cmos Process ◽

Sleeping Time ◽

Time Control ◽

Soft Start ◽

Light Load ◽

Near Threshold

A novel near-threshold voltage startup monolithic boost converter is presented in this paper using an adaptive sleeping time control (ASTC) scheme for low-power applications. The proposed ASTC scheme can promote the power efficiency of the current-mode boost converter under light load by automatically adjusting the sleep time of the converter, and the converter's quiescent current drops down to 4[Formula: see text][Formula: see text]A during the sleeping period. In addition, a new soft-start method is introduced to make the boost converter start up with a near-threshold input voltage. The proposed boost converter was fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS process and occupies a small chip area of 0.50[Formula: see text][Formula: see text][Formula: see text]mm. Experimental results show that the boost converter achieves the minimum 0.5-V startup voltage when the output voltage is set to 1.8[Formula: see text]V. After startup, the input voltage range can be expanded from 0.3[Formula: see text]V to 1.5[Formula: see text]V with a switching frequency of 1[Formula: see text]MHz. In addition, a peak efficiency of 94% and a minimum efficiency of 81% are measured at the 1.5-V input voltage as the load current ranges from 0.1[Formula: see text]mA to 100[Formula: see text]mA.

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A soft-start Pulse Frequency Modulation-controlled boost converter for low-power applications

Electronics and Electrical Engineering ◽

10.1201/b18443-33 ◽

2015 ◽

pp. 173-178

Keyword(s):

Low Power ◽

Frequency Modulation ◽

Pulse Frequency ◽

Boost Converter ◽

Pulse Frequency Modulation ◽

Soft Start

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A Digital–Controlled Soft-Start Circuit for Negative Output DC–DC Converter

Journal of Circuits System and Computers ◽

10.1142/s0218126619500671 ◽

2019 ◽

Vol 28 (04) ◽

pp. 1950067 ◽

Cited By ~ 1

Author(s):

Yan-Ming Li ◽

Xiao-Li Xi ◽

Hao Zhang ◽

Zhong-Hui Chen ◽

Jian Sun ◽

...

Keyword(s):

Simple Structure ◽

High Reliability ◽

Boost Converter ◽

Inrush Current ◽

Digital To Analog Converter ◽

Soft Start ◽

Voltage Output ◽

Voltage Drops ◽

Start Up ◽

Analog Converter

To suppress the inrush current and overshoot voltage generated at the start-up stage of Buck–Boost converter, a digital–controlled soft-start circuit based on digital-to-analog converter (DAC) control technology is proposed in this paper. The power consumption of the circuit is zero and the circuit is also keeps the characteristics of simple structure and high reliability. The circuit has been integrated into a Buck–Boost converter with negative voltage output by using the 0.18[Formula: see text][Formula: see text]m CDMOS high voltage process. The experimental results show that this circuit can effectively suppress the rush current, and the output voltage drops smoothly from 0 to the adjustment value, [Formula: see text][Formula: see text]V.

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