Linearity improvement of double differential pair CMOS OTA using quasi-floating-gate technique

2012 ◽  
Author(s):  
Shankar Narayan ◽  
Vijaya Bhadauria
Keyword(s):  
Floating Gate ◽  
Linearity Improvement ◽  
Differential Pair

scholarly journals A VGA Linearity Improvement Technique for ECG Analog Front-End in 65nm CMOS

2019 ◽  
Vol 29 (07) ◽  
pp. 2050113
Author(s):  
Rajasekhar Nagulapalli ◽  
Khaled Hayatleh ◽  
Steve Barker
Keyword(s):  
Dynamic Range ◽  
Current Source ◽  
Harmonic Distortion ◽  
Loop Gain ◽  
Silicon Area ◽  
Front End ◽  
Analog Front End ◽  
Linearity Improvement ◽  
Local Feedback ◽  
Differential Pair

This paper presents a 65[Formula: see text]nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5–100[Formula: see text]mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loop-gain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25–50 dB gain, and post-layout simulations showed a 15[Formula: see text]dB reduction in the harmonic distortion for 20[Formula: see text]mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108[Formula: see text][Formula: see text]m2 silicon area and consumes 0.43 [Formula: see text]A from a 1.2[Formula: see text]V power supply.

Linearity Improvement of Bulk Driven Floating Gate OTA Using Cross-Bulk and Quasi-Bulk Techniques

2020 ◽  
pp. 2150124
Author(s):  
Tanmay Dubey ◽  
Vijaya Bhadauria
Keyword(s):  
Input Signal ◽  
Cross Coupling ◽  
Monte Carlo Analysis ◽  
Floating Gate ◽  
Cmos Design ◽  
Linearity Improvement ◽  
Floating Gate Mosfets ◽  
The Cost ◽  
Linear Voltage ◽  
Linearization Techniques

In this paper, two highly linear OTAs are presented using a combination of three linearization techniques: floating gate, bulk driven, and source degeneration. In the first OTA, bulk driven floating gate MOSFETs are used as input transistors. The input signal given at the bulk terminals of these input transistors are in the opposite phase of the input signal provided to one of the gates of the respective floating gate MOSFET. This cross-coupling method resulted in a highly linear voltage-to-current conversion at the cost of reduced transconductance. In the second proposed OTA, this reduction in transconductance is restored by using novel quasi-bulk floating gate MOSFETs as input transistors while maintaining the improved linearity. Both the OTAs are designed and simulated using 180 nm CMOS design library and powered with [Formula: see text]0.5[Formula: see text]V dual power supply. The process variation and mismatch effects on both the OTAs are examined using corner and Monte Carlo analysis. The layouts of the proposed OTAs are also presented and workability is confirmed using post-layout simulations.

Carrier Profiling of the 10-nm-order Structure in a 3D Flash Memory Cell Using Scanning Nonlinear Dielectric Microscopy

2019 ◽  
Author(s):  
Jun Hirota ◽  
Ken Hoshino ◽  
Tsukasa Nakai ◽  
Kohei Yamasue ◽  
Yasuo Cho
Keyword(s):  
Spatial Resolution ◽  
Flash Memory ◽  
Analytical Techniques ◽  
Memory Cell ◽  
Memory Device ◽  
Floating Gate ◽  
Order Structure ◽  
Carrier Distribution ◽  
Nonlinear Dielectric ◽  
Flash Memory Cell

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

Investigations of Leakage Paths in Sub-0.35μm DRAM Products Using Advanced Focused Ion Beam Techniques

1998 ◽  
Author(s):  
H. Lorenz ◽  
C. Engel
Keyword(s):  
Focused Ion Beam ◽  
Cell Function ◽  
Dielectric Breakdown ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Floating Gate ◽  
Leakage Path ◽  
Contrast Technique ◽  
Voltage Contrast

Abstract Due to the continuously decreasing cell size of DRAMs and concomitantly diminishing thickness of some insulating layers new failure mechanisms appear which until now had no significance for the cell function. For example high resistance leakage paths between closely spaced conductors can lead to retention problems. These are hard to detect by electrical characterization in a memory tester because the involved currents are in the range of pA. To analyze these failures we exploit the very sensitive passive voltage contrast of the Focused Ion Beam Microscope (FIB). The voltage contrast can further be enhanced by in-situ FIB preparations to obtain detailed information about the failure mechanism. The first part of this paper describes a method to detect a leakage path between a borderless contact on n-diffusion and an adjacent floating gate by passive voltage contrast achieved after FIB circuit modification. In the second part we will demonstrate the localization of a DRAM trench dielectric breakdown. In this case the FIB passive voltage contrast technique is not limited to the localization of the failing trench. We can also obtain the depth of the leakage path by selective insitu etching with XeF2 stopped immediately after a voltage contrast change.

Floating Gate Memory Based on Ferritin Nanodots with High-kGate Dielectrics

2009 ◽  
Vol 48 (4) ◽  
pp. 04C153 ◽  
Author(s):  
Kosuke Ohara ◽  
Yukiharu Uraoka ◽  
Takashi Fuyuki ◽  
Ichiro Yamashita ◽  
Toshitake Yaegashi ◽  
...  
Keyword(s):  
Floating Gate ◽  
Floating Gate Memory
Sign in / Sign up

Export Citation Format

Share Document