Investigations of Leakage Paths in Sub-0.35μm DRAM Products Using Advanced Focused Ion Beam Techniques

Author(s):  
H. Lorenz ◽  
C. Engel

Abstract Due to the continuously decreasing cell size of DRAMs and concomitantly diminishing thickness of some insulating layers new failure mechanisms appear which until now had no significance for the cell function. For example high resistance leakage paths between closely spaced conductors can lead to retention problems. These are hard to detect by electrical characterization in a memory tester because the involved currents are in the range of pA. To analyze these failures we exploit the very sensitive passive voltage contrast of the Focused Ion Beam Microscope (FIB). The voltage contrast can further be enhanced by in-situ FIB preparations to obtain detailed information about the failure mechanism. The first part of this paper describes a method to detect a leakage path between a borderless contact on n-diffusion and an adjacent floating gate by passive voltage contrast achieved after FIB circuit modification. In the second part we will demonstrate the localization of a DRAM trench dielectric breakdown. In this case the FIB passive voltage contrast technique is not limited to the localization of the failing trench. We can also obtain the depth of the leakage path by selective insitu etching with XeF2 stopped immediately after a voltage contrast change.

Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.


Author(s):  
X. Yang ◽  
X. Song

Abstract Novel Focused Ion Beam (FIB) voltage-contrast technique combined with TEM has been used in this study to identify a certain subtle defect mechanism that caused reliability stress failures of a new product. The suspected defect was first isolated to a unique via along the row through electrical testing and layout analysis. Static voltage contrast of FIB cross-section was used to confirm the suspected open defect at the via. Precision Transmission Electron Microscope (TEM) was then used to reveal the detail of the defect. Based on the result, proper process changes were implemented. The failure mode was successfully eliminated and the reliability of the product was greatly improved.


Author(s):  
P. Perdu ◽  
G. Perez ◽  
M. Dupire ◽  
B. Benteo

Abstract To debug ASIC we likely use accurate tools such as an electron beam tester (Ebeam tester) and a Focused Ion Beam (FIB). Interactions between ions or electrons and the target device build charge up on its upper glassivation layer. This charge up could trigger several problems. With Ebeam testing, it sharply decreases voltage contrast during Image Fault Analysis and hide static voltage contrast. During ASIC reconfiguration with FIB, it could induce damages in the glassivation layer. Sample preparation is getting a key issue and we show how we can deal with it by optimizing carbon coating of the devices. Coating is done by an evaporator. For focused ion beam reconfiguration, we need a very thick coating. Otherwise the coating could be sputtered away due to imaging. This coating is use either to avoid charge-up on glassivated devices or as a sacrificial layer to avoid short circuits on unglassivated devices. For electron beam Testing, we need a very thin coating, we are now using an electrical characterization method with an insitu control system to obtain the right thin thickness. Carbon coating is a very cheap and useful method for sample preparation. It needs to be tuned according to the tool used.


Author(s):  
S.L. Ting ◽  
P.K. Tan ◽  
I. Withana ◽  
H. Tan ◽  
C.Q. Chen

Abstract Passive voltage contrast (PVC) is widely used to detect underlying connectivity issues between metals based on the brightness of upper metals using scanning electron microscopy (SEM) or focused ion beam (FIB). [1] However, it cannot be applied in all cases due to the uniqueness of each case where brightness alone is insufficient to tell leakage location. In this study, propose a simple technique using platinum (Pt) marking as a circuit edit (CE) technique to alter metal PVC to identify the actual leakage location. Conventional SEM and PVC contrast imaging are unable to pinpoint exact defects without data confirming the leakage from nano-probing such as Atomic Force Probing (AFP) or SEM base nano-probing (NP) [2]. Using this method, we can improve the analysis cycle time by direct analysts the defective location in SEM, while also saving tool cost.


Author(s):  
Hagit Barda ◽  
Irina Geppert ◽  
Avraham Raz ◽  
Rémy Berthier

Abstract An experimental setup is presented, that allows in-situ Transition Electron Microscopy (TEM) investigation of void formation and growth within fully embedded interconnect structure, as a response to an external bias. A special TEM holder is employed to perform in-situ I-V measurements across the Via, simultaneously monitoring the morphological and chemical changes surrounding the void. This work presents in detail a Focused Ion Beam (FIB) based sample preparation method that allows the analysis of a Cu single Via structure found in the advanced microelectronic 14nm FinFET technology, as well as preliminary TEM observations.


1998 ◽  
Author(s):  
Romain Desplats ◽  
Jamel Benbrik ◽  
Philippe Perdu ◽  
Bruno Benteo ◽  
François Marc ◽  
...  

Abstract Recent planar technologies with 3 metal layers or more challenge current physical design modification capacities using Focused Ion Beam tools. Image visibility on the FIB is drastically reduced, making accurate positioning and milling operations in the area of interest more difficult, and the use of power planes increases the risk of short circuits while accessing inferior metal lines. Despite the complexity of FIB modifications, however, the demand for circuit modifications continues to increase. To respond to this demand for successful, time efficient, FIB modifications, step by step monitoring of operations is imperative. In this paper, we will present an innovative method which brings in-situ electrical monitoring and contactless measurement capabilities to FIB systems. Electrical connection of the circuit inside the vacuum FIB chamber is done using a commercial load module and logic waveform acquisition with the FIB is obtained without modifying FIB hardware using a voltage contrast approach. With this method, it is possible to verify the completion of FIB milling and depositing operations by temporarily suspending FIB action so that a test pattern can be run allowing electrical testing and measurements of the circuit without damaging it.


Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.


Author(s):  
Natsuko Asano ◽  
Shunsuke Asahina ◽  
Natasha Erdman

Abstract Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.


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