Performance analysis of power gating designs in low power VLSI circuits

2011 ◽  
Author(s):  
C. Chrisjin Gnana Suji ◽  
S. Maragatharaj ◽  
R. Hemima
Keyword(s):  
Performance Analysis ◽  
Low Power ◽  
Vlsi Circuits ◽  
Power Gating

Power gating of VLSI circuits using MEMS switches in low power applications

2011 ◽  
Author(s):  
Hosam Shobak ◽  
Mohamed Ghoneim ◽  
Nawal El Boghdady ◽  
Sarah Halawa ◽  
Sophinese Iskander ◽  
...  
Keyword(s):  
Low Power ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Mems Switches

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Integration ◽  
2017 ◽  
Vol 57 ◽  
pp. 108-124 ◽  
Author(s):  
Mahshid Mojtabavi Naeini ◽  
Sreedharan Baskara Dass ◽  
Chia Yee Ooi ◽  
Tomokazu Yoneda ◽  
Michiko Inoue
Keyword(s):  
Low Power ◽  
Power Reduction ◽  
Power Gating ◽  
Scan Test

scholarly journals Performance Analysis of Routing Protocol for Low Power and Lossy Networks (RPL) in Large Scale Networks

2017 ◽  
Vol 4 (6) ◽  
pp. 2172-2185 ◽  
Author(s):  
Xiyuan Liu ◽  
Zhengguo Sheng ◽  
Changchuan Yin ◽  
Falah Ali ◽  
Daniel Roggen
Keyword(s):  
Performance Analysis ◽  
Low Power ◽  
Routing Protocol ◽  
Large Scale ◽  
Lossy Networks ◽  
Large Scale Networks

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

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