scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

scholarly journals Design and Implementation of Energy Efficient Power Gated MALFA Cell

2019 ◽  
Vol 8 (4) ◽  
pp. 1178-1181
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Full Adder ◽  
Power Reduction ◽  
Power Gating ◽  
Hybrid Power ◽  
Reduction Techniques ◽  
Hybrid Cmos ◽  
Adiabatic Logic ◽  
Efficient Power

Power gating is one of the power reduction techniques that is mostly suitable for low power VLSI applications. It reduces the power consumption by shutting of the current to the blocks not in use. Hybrid power gating is applied to Modified Adiabatic Logic based Full Adder (ALFA) cell. The proposed ALFA cell reduces the energy consumption by 67.21%, 51.31%, 55.86% and 27.01% when compared to CMOS FA, PTL with TG 16T, hybrid CMOS and PTL with TG 14T. ALFA cell with hybrid power gating technique reduces the power consumption by 1.76, 2.08%, 1.13%, 1.44%, 0.48% and delay by 5.92%, 11.19%, 11.19%, 5.92%, 24.92% when compared to ALFA cell with NMOS sleepy approach, PMOS sleepy approach, PMOS sleepy stack approach, NMOS sleepy stack approach and dual stack approach.

scholarly journals Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology

2019 ◽  
Vol 14 (2) ◽  
pp. 912
Author(s):  
Woo Wei Kai ◽  
Nabihah Ahmad ◽  
Mohamad Hairol Jabbar
Keyword(s):  
Low Power ◽  
Average Power ◽  
Full Adder ◽  
Oxide Thickness ◽  
Low Complexity ◽  
Operating Voltage ◽  
Short Channel ◽  
Static Power ◽  
Subthreshold Leakage ◽  
Power Delay Product

In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of  supply. The result showed the reduction of VBB technique in term of peak power,  and average power,   compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.

A HIGH-LEVEL TECHNIQUE FOR ESTIMATION AND OPTIMIZATION OF LEAKAGE POWER FOR FULL ADDER

2013 ◽  
Vol 12 (02) ◽  
pp. 1350011
Author(s):  
JAYRAM SHRIVAS ◽  
SHYAM AKASHE ◽  
NITESH TIWARI
Keyword(s):  
Leakage Current ◽  
Power Supply ◽  
Low Voltage ◽  
Full Adder ◽  
Leakage Power ◽  
Power Gating ◽  
Sleep Transistors ◽  
Power Application ◽  
High Level ◽  
Standby Mode

Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.

scholarly journals Two state-of-the-arts current-mode ternary full adders based on CNTFET Technology

2020 ◽  
Vol 9 (1) ◽  
pp. 19
Author(s):  
Mona Moradi
Keyword(s):  
Power Dissipation ◽  
Digital Signal ◽  
Current Mode ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Digital Signal Processors ◽  
The Arts ◽  
Threshold Voltages ◽  
Static Power ◽  
Signal Processors

Adder core respecting to its various applications in VLSI circuits and<br />systems is considered as the most critical building block in microprocessors,<br />digital signal processors and arithmetic operations. Novel designs of a low<br />power and complexity Current Mode 1-bit Full Adder cell based on<br />CNTFET technology has been presented in this paper. Three major parts<br />construct their structures; 1) the first part that converts current to voltage; 2)<br />threshold detectors (TD); and 3) parallel paths to convey the output currents<br />flow. Adjusting threshold voltages which are significant factor for setting<br />threshold detectors switching point has been achieved by means of CNTFET<br />technology. It would bring significant improvements in adjusting threshold<br />voltages, regarding to its unique characterizations. Simple design, less<br />transistor counts and static power dissipation and better performance<br />comparing previous designs could be considered as some advantages of the<br />novel designs.

Leakage Power Reduction in 32-bit Digital Comparator Using Modified Power Gating Technique

2015 ◽  
Vol 742 ◽  
pp. 741-744 ◽  
Author(s):  
G. Amuthavalli ◽  
R. Gunasundari ◽  
A. Nijandan
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Channel Length ◽  
Power Reduction ◽  
Leakage Power ◽  
Power Gating ◽  
Dynamic Power ◽  
Digital Comparator ◽  
Static Power ◽  
Scaling Down

As scaling down of CMOS transistor’s channel length is done for miniaturization, the design community primarily focuses on the high performance & power-aware design. The power consumption of any circuit solely holds the performance and the life of it. But static power consumption deteriorates them and dominates the dynamic power consumption because of its leakage components. A modified approach of pulse triggering in the Power Gating technique called MPG (Modified Power Gating) is proposed to reduce the static power consumption (leakage power) of digital subsystems. Sub threshold leakage power of MPG Inverter (INV) and 32-bit Digital Comparator (DC) is analyzed and reduced with 35% to 40% leakage savings compared with conventional and existing techniques by simulating it in Cadence GPDK.

scholarly journals Transistor sizing of CMOS VLSI Circuits in Deep Submicron Technology

2019 ◽  
Vol 8 (11S2) ◽  
pp. 15-29
Keyword(s):  
Full Adder ◽  
Deep Submicron ◽  
Vlsi Circuits ◽  
Total Power ◽  
Cmos Inverter ◽  
Transistor Sizing ◽  
Cmos Vlsi

In Very-huge scale reconciliation (VLSI) application zone, postponement and power are the significant variables for any advanced circuits. Its observed that the as CMOS Inverter Transistor Size decreases from 1µm to 120nm, power reduced from 3.331 to 2.644 (µW) and delay reduced from 5.026 to 22.66 (pS). It is observed that the table 4 as 28T Full Adder Circuit Voltage Scale decreases from 5 V to 1 V, Total power reduced from 63150 to 2262 (nW) and delay reduced from 39.93 to 38.52 (nS) in 180nm technology. It is observed that the table 6 as 28T Full Adder Circuit Voltage Scale decreases from 2 V to 0.8 V, Total power reduced from 21.39 to 2.916 (µW) and delay reduced from 4.939 to 4.74 (nS) in 90nm technology. It is observed that the table 8 as 28T Full Adder Circuit Voltage Scale decreases from 1.5 V to 0.7 V, Total power reduced from 8.98 to 1.713 (µW) and delay reduced from 4.963 to 4.581 (nS) in 45nm technology.

scholarly journals Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power

2017 ◽  
Vol 7 (6) ◽  
pp. 3010
Author(s):  
Woo Wei Kai ◽  
Nabihah binti Ahmad ◽  
Mohamad Hairol Bin Jabbar
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Threshold Voltage ◽  
Average Power ◽  
Vlsi Design ◽  
Full Adder ◽  
Oxide Thickness ◽  
Conventional Technique ◽  
Body Biasing ◽  
Static Power

The static power consumption is an important parameter concern in IC design due to t for a higher integration numbers of transistor to achieve greater performance in a single chip. Leakage current is the main issues for static power dissipation in standby mode as the size of transistor been scale. Therefore, the subthreshold leakage current rises due to threshold voltage scaling and gate leakage current increases due to scale down of oxide thickness. In this paper, a Variable Body Biasing (VBB) technique was applied to reduce static power consumption in VLSI design. The VBB technique used a DC bias at body terminal to control the threshold voltage efficiently. The Synopsys Custom Designer EDA tools in 90nm MOSFET technology was used to design a 1-bit full adder with VBB technique in full custom methodology. The simulation of 1-bit full adder was carried out with operation voltage   supply was compared in conventional technique and VBB technique. The results achieved the reduction in term of peak power,   and average power,   in static CMOS 1-bit full adder compared with conventional bias and VBB technique.

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