Low Leakage Zero Ground Bounce Noise Nanoscale Full Adder Using Source Biasing Technique

2019 ◽  
Vol 14 (3) ◽  
pp. 360-370
Author(s):  
Candy Goyal ◽  
Jagpal Singh Ubhi ◽  
Balwinder Raj
Keyword(s):  
Full Adder ◽  
Low Leakage ◽  
Ground Bounce

scholarly journals NOVEL GROUND BOUNCE NOISE REDUCTION WITH ENHANCED POWER AND AREA EFFICIENCY FOR LOW POWER PORTABLE APPLICATION

2013 ◽  
pp. 280-282
Author(s):  
MOHD ABDUL SUMER ◽  
KADIYAM TIRUMALA RAO ◽  
PADALA SRINIVAS
Keyword(s):  
Mobile Applications ◽  
Heat Dissipation ◽  
Full Adder ◽  
Logic Circuits ◽  
Analysis And Design ◽  
Complex Arithmetic ◽  
Area Efficiency ◽  
Low Leakage ◽  
Adiabatic Logic ◽  
Ground Bounce

As technology scales into the nanometer regime ground bounce noise and heat dissipation immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit PFAL full adder cells are proposed for mobile applications with low ground bounce noise and heat dissipation in the circuits using adiabatic logic. The simulations are done using DSCH &MicrowindSoftware.

scholarly journals Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

2013 ◽  
Vol 2013 ◽  
pp. 1-13 ◽  
Author(s):  
Farid Moshgelani ◽  
Dhamin Al-Khalili ◽  
Côme Rozon
Keyword(s):  
Work Function ◽  
Leakage Current ◽  
Power Supply ◽  
Full Adder ◽  
Arithmetic Circuits ◽  
University Of Florida ◽  
Low Leakage ◽  
The University

We are examining different configurations and circuit topologies for arithmetic components such as adder and compressor circuits using both symmetric and asymmetric work-function FinFETs. Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50%, respectively, compared to results in the literature. For the 14-transistor (14T) full adder topology, both leakage and delay are decreased by 23% and 29%, respectively, compared to the mirror topology. The 14T adder topology, using asymmetric devices without any additional power supply, achives reduction in leakage current by 85% with a small degradation of 7% in delay. The compressor circuits, using asymmetric devices for one of the proposed configurations, achieve reduction in both leakage current and delay by 86% and 4%, respectively. All simulations are based on a 25 nm FinFET technology using the University of Florida UFDG model.

scholarly journals Design and Performasnce Analysis of Hybrid Full Adder Using Finfet 40nm Technology

2019 ◽  
Vol 8 (6) ◽  
pp. 4521-4525
Keyword(s):  
Performance Analysis ◽  
Energy Efficient ◽  
Full Adder ◽  
Propagation Delay ◽  
Leakage Power ◽  
Drive Current ◽  
Internal Logic ◽  
Low Leakage ◽  
Cadence Tool ◽  
Power And Energy

Designing a low power and energy efficient circuits in FinFET technology is of great Challenge. This paper presents the internal logic structure and circuit operation using the devices, CMOS and FinFETs for designing the hybrid adder cells. At transistor level, CMOS and FinFET based hybrid full adder (HFA) and improved hybrid full adder (IHFA) is designed. Simulations are carried out using the cadence tool in UMC 40nm and the performance analysis of these HFA and IHFA are compared with the 40nm FinFET technology. It is observed that IHFA is better when compared with the HFA in terms of propagation delay, power consumption and energy delay product. IHFA achieves the higher drive current and low leakage power for better mobility and transistor scaling as compared with HFA.

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

A New Keeper Domino Logic Based Full Adder for High Speed Arithmetic Circuits

2020 ◽  
Vol 12 ◽  
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Ajay Kumar ◽  
Brahamdeo Prasad Singh
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Efficiency ◽  
Dynamic Logic ◽  
Full Adder ◽  
Leakage Power ◽  
Low Leakage ◽  
Dynamic Circuits ◽  
Power Delay Product ◽  
Domino Circuits

Objective: A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve power delay product of the dynamic logic using carbon nanotube MOSFET. Method: As a benchmark, an one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature. Result: The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40% respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using SiMOSFET and CN-MOSFET technologies. Conclusion: A comparison of the proposed keeper with previously published designs is also given in terms of power consumption, delay and power delay product with the improvement up to 75, 18 and 50% respectively. The proposed circuit uses only two transistors, so it requires less area and gives high efficiency.

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