A 2.5-GHz Optical Receiver Front-end in a 0.13 μm CMOS Process for Biosensor Application

2018 ◽  
Author(s):  
Suhaila Isaak ◽  
Yusmeeraz Yusof ◽  
Leong Choon Wei
Keyword(s):  
Optical Receiver ◽  
Cmos Process ◽  
Front End ◽  
Biosensor Application

A 10-Gb/s 0.18-μm CMOS Optical Receiver Front-End Amplifier

2013 ◽  
Vol 760-762 ◽  
pp. 115-119
Author(s):  
Wen Yuan Li ◽  
Rui Guo
Keyword(s):  
Low Voltage ◽  
Low Cost ◽  
Parasitic Capacitance ◽  
Optical Receiver ◽  
Cmos Process ◽  
Chip Area ◽  
Noise Interference ◽  
Limiting Amplifier ◽  
Front End ◽  
Voltage Swing

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is stimulation using a 0.18μm CMOS process. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The tiny photo current received by the receiver AFE is amplified to voltage swing of 400. The results indicate that, with a photodiode parasitic capacitance of 500fF and the bonding pad parasitic capacitance of 200fF between which a 2-mm bond wire is inserted at the input node, the AFE provides a conversion gain of up to 89.21 dB and 3 dB bandwidth of 9.78 GHz. Operating under a 1.8V supply, circuit power dissipation is 95 mW and its sensitivity is 18.5μA for BER of 10-12

Design and analysis of a single HBT-based optical receiver front-end

2005 ◽  
Vol 49 (8) ◽  
pp. 1396-1404 ◽  
Author(s):  
P. Chakrabarti ◽  
P. Kalra ◽  
S. Agrawal ◽  
G. Gupta ◽  
N. Menon
Keyword(s):  
Optical Receiver ◽  
Front End

Design of a Digital Baseband Processor for UHF Tags

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2060
Author(s):  
Na Bai ◽  
Liang Wang ◽  
Yaohua Xu ◽  
Yi Wang
Keyword(s):  
Data Processing ◽  
Low Voltage ◽  
Random Number Generator ◽  
Digital Circuit ◽  
Cmos Process ◽  
Front End ◽  
Rf Front End ◽  
Machine Module ◽  
Baseband Processor ◽  
Digital Baseband

In this paper, we present a new digital baseband processor for UHF tags. It is a low-power and low-voltage digital circuit and adopts the Chinese military standard protocol GJB7377.1. The processor receives data or commands from the RF front-end and carries out various functions, such as receiving and writing data to memory, reading and sending memory data to the RF front-end and killing tags. The processor consists of thirteen main sub-modules: TPP decoding, clock management, random number generator, power management, memory controller, cyclic redundancy check, FM0 encoding, input data processing, output data processing, command detection module, initialization module, state machine module and controller. We use ModelSim for the TPP decoding simulation and communication simulation between tag and reader, and the simulation results meet the design requirements. The processor can be applied to UHF tags and has been taped out using a TSMC 0.18 um CMOS process.

scholarly journals 14.85 µW Analog Front-End for Photoplethysmography Acquisition with 142-dBΩ Gain and 64.2-pArms Noise

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 512
Author(s):  
Binghui Lin ◽  
Mohamed Atef ◽  
Guoxing Wang
Keyword(s):  
Dynamic Range ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Control Block ◽  
Silicon Area ◽  
Front End ◽  
Analog Front End

A low-power, high-gain, and low-noise analog front-end (AFE) for wearable photoplethysmography (PPG) acquisition systems is designed and fabricated in a 0.35 μm CMOS process. A high transimpedance gain of 142 dBΩ and a low input-referred noise of only 64.2 pArms was achieved. A Sub-Hz filter was integrated using a pseudo resistor, resulting in a small silicon area. To mitigate the saturation problem caused by background light (BGL), a BGL cancellation loop and a new simple automatic gain control block are used to enhance the dynamic range and improve the linearity of the AFE. The measurement results show that a DC photocurrent component up-to-10 μA can be rejected and the PPG output swing can reach 1.42 Vpp at THD < 1%. The chip consumes a total power of 14.85 μW using a single 3.3-V power supply. In this work, the small area and efficiently integrated blocks were used to implement the PPG AFE and the silicon area is minimized to 0.8 mm × 0.8 mm.

Multi-Rate Low-Noise Optical Receiver Front-End

2020 ◽  
Vol 38 (18) ◽  
pp. 4978-4986
Author(s):  
Dan Li ◽  
Gabriele Minoia ◽  
Matteo Repossi ◽  
Daniele Baldi ◽  
Enrico Temporiti ◽  
...  
Keyword(s):  
Low Noise ◽  
Optical Receiver ◽  
Front End
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