scholarly journals 14.85 µW Analog Front-End for Photoplethysmography Acquisition with 142-dBΩ Gain and 64.2-pArms Noise

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 512
Author(s):  
Binghui Lin ◽  
Mohamed Atef ◽  
Guoxing Wang
Keyword(s):  
Dynamic Range ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Control Block ◽  
Silicon Area ◽  
Front End ◽  
Analog Front End

A low-power, high-gain, and low-noise analog front-end (AFE) for wearable photoplethysmography (PPG) acquisition systems is designed and fabricated in a 0.35 μm CMOS process. A high transimpedance gain of 142 dBΩ and a low input-referred noise of only 64.2 pArms was achieved. A Sub-Hz filter was integrated using a pseudo resistor, resulting in a small silicon area. To mitigate the saturation problem caused by background light (BGL), a BGL cancellation loop and a new simple automatic gain control block are used to enhance the dynamic range and improve the linearity of the AFE. The measurement results show that a DC photocurrent component up-to-10 μA can be rejected and the PPG output swing can reach 1.42 Vpp at THD < 1%. The chip consumes a total power of 14.85 μW using a single 3.3-V power supply. In this work, the small area and efficiently integrated blocks were used to implement the PPG AFE and the silicon area is minimized to 0.8 mm × 0.8 mm.

scholarly journals Expanding Bias-instability of MEMS Silicon Oscillating Accelerometer Utilizing AC Polarization and Self-Compensation

Sensors ◽  
2020 ◽  
Vol 20 (5) ◽  
pp. 1455
Author(s):  
Yang Zhao ◽  
Guoming Xia ◽  
Qin Shi ◽  
Anping Qiu
Keyword(s):  
Dynamic Range ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Micro Electro Mechanical System ◽  
Low Noise ◽  
Experimental Result ◽  
Front End ◽  
Compensation Technique ◽  
Bias Instability ◽  
Gate Size

This paper presents a MEMS (Micro-Electro-Mechanical System) Silicon Oscillating Accelerometer (SOA) with AC (alternating current) polarization to expand its bias-instability limited by the up-converted 1/f noise from front-end transimpedance amplifier (TIA). In contrast to the conventional DC (direct current) scheme, AC polarization breaks the trade-off between input transistor gate size and white noise floor of TIA, a relative low input loading capacitance can be implemented for low noise consideration. Besides, a self-compensation technique combining polarization source and reference in automatic-gain-control (AGC) is put forward. It cancels the 1/f noise and drift introduced by the polarization source itself, which applies to both DC and AC polarization cases. The experimental result indicates the proposed AC polarization and self-compensation strategy expand the bias-instability of studied SOA from 2.58 μg to 0.51 μg with a full scale of ± 30 g, a 155.6 dB dynamic range is realized in this work.

High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design

2013 ◽  
Vol 284-287 ◽  
pp. 2647-2651
Author(s):  
Zhe Yang Huang ◽  
Che Cheng Huang ◽  
Jung Mao Lin ◽  
Chung Chih Hung
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Chip Area ◽  
Wireless Receiver ◽  
Front End ◽  
Total Power Consumption

This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm2 including dummy and pads.

scholarly journals A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis

2018 ◽  
Vol 8 (3) ◽  
pp. 27 ◽  
Author(s):  
Avish Kosari ◽  
Jacob Breiholz ◽  
NingXi Liu ◽  
Benton Calhoun ◽  
David Wentzloff
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Low Noise ◽  
Signal Acquisition ◽  
Cmos Process ◽  
Ecg Signal ◽  
Ecg Monitoring ◽  
Power Circuit ◽  
Front End ◽  
Analog Front End

This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications.

scholarly journals 22nm FINFET Based High Gain Wide Band Differential Amplifier

2021 ◽  
Vol 15 ◽  
pp. 55-62
Author(s):  
G Vasudeva ◽  
Uma B. V.
Keyword(s):  
Performance Metrics ◽  
Dynamic Range ◽  
High Gain ◽  
Low Noise ◽  
Vlsi Circuits ◽  
Differential Amplifier ◽  
Model Parameters ◽  
Front End ◽  
Analog Front End ◽  
High K

Differential Amplifier is a primary building block of analog and mixed signal circuit for pre-processing and signal conditioning of analog signal. FINFET devices with high-k gate oxide at 22nm technology are predominantly used for high speed and low power complex VLSI circuits. FINFET based differential amplifiers are widely used in ADC’s and signal Processing applications due to their advantages in terms of power dissipation. Analog front end of complex VLSI circuits need to offer high gain, higher stability and low noise figure. Designing of FINFET based VLSI sub-circuits requires proper design procedure that can provide designers flexibility in controlling the circuit performances. In this paper, differential amplifier is designed using model parameters of high-k FINFET in 22nm technology. The conventional procedures for designing MOSFET based differential amplifier are modified for designing FINFET based differential amplifier. Schematic capture is carried out in Cadence environment and simulations are obtained considering 22nm FINFET PDK. The performance metrics are evaluated and optimized considering multiple iterations. The designed differential amplifier has slew rate of 6V/µSec and settling time of 0.9 µSec which is a desired metric for ADCs. Power Supply Rejection Ratio (PSRR) is 83 dB and dynamic range is 1.6754 V. Open loop DC gain of DA is achieved to be 103 dB with phase margin of 630 that demonstrates the advantages of DA designed in this work suitable for analog front end

scholarly journals Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays

Sensors ◽  
2020 ◽  
Vol 20 (4) ◽  
pp. 1205 ◽  
Author(s):  
Iván Zamora ◽  
Eyglis Ledesma ◽  
Arantxa Uranga ◽  
Núria Barniol
Keyword(s):  
Integrated Circuit ◽  
Imaging System ◽  
Ultrasonic Transducer ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Axial Distance ◽  
Cmos Integrated Circuit ◽  
Front End ◽  
Analog Front End

This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.

A Charge Amplifier Based Complementary Metal–Oxide–Semiconductor Analog Front End for Piezoelectric Microphones in Hearing Aid Devices

2019 ◽  
Vol 15 (3) ◽  
pp. 315-322
Author(s):  
Manu Chilukuri ◽  
Sungyong Jung ◽  
Hoon-Ju Chung
Keyword(s):  
Hearing Aid ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Charge Amplifier ◽  
Front End ◽  
Analog Front End ◽  
A Charge ◽  
Cascode Current Mirror

In this paper, a low noise and low power analog front end for piezoelectric microphones used in hearing aid devices is presented. It consists of a Charge Amplifier, followed by a Variable Gain Amplifier and an Analog-to-Digital Converter. At the core of charge amplifier a two stage opamp with modified cascode current mirror is designed which achieves a gain of 93 dB and phase margin of 62°. Designed analog front end achieves an input referred noise of 0.12 μVrms and SNR of 74 dB. It consumes power of 430 μW from 1.8 V supply and occupies an area of 1.2 mm × 0.22 mm. Proposed circuit is designed and fabricated in 0.18 μm CMOS process. Designed circuit is interfaced with a sensor model of piezoelectric microphone, which mimics Ormia ochracea's auditory system, and its performance is successfully verified against simulation results.

scholarly journals A VGA Linearity Improvement Technique for ECG Analog Front-End in 65nm CMOS

2019 ◽  
Vol 29 (07) ◽  
pp. 2050113
Author(s):  
Rajasekhar Nagulapalli ◽  
Khaled Hayatleh ◽  
Steve Barker
Keyword(s):  
Dynamic Range ◽  
Current Source ◽  
Harmonic Distortion ◽  
Loop Gain ◽  
Silicon Area ◽  
Front End ◽  
Analog Front End ◽  
Linearity Improvement ◽  
Local Feedback ◽  
Differential Pair

This paper presents a 65[Formula: see text]nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5–100[Formula: see text]mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loop-gain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25–50 dB gain, and post-layout simulations showed a 15[Formula: see text]dB reduction in the harmonic distortion for 20[Formula: see text]mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108[Formula: see text][Formula: see text]m2 silicon area and consumes 0.43 [Formula: see text]A from a 1.2[Formula: see text]V power supply.

Sign in / Sign up

Export Citation Format

Share Document